Amaury Nève

Influence of device engineering on the analog and RF performances of SOI MOSFETs

This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFETs with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).

Fully-Depleted SOI CMOS Technology for Heterogeneous Micropower, High-Temperature or RF Microsystems

Based on an extensive review of research results on the material, process, device and circuit properties of thin-film fully depleted SOI CMOS, our work demonstrates that such a process with channel lengths of about 1 mum may emerge as a most promising and mature contender for integrated microsystems which must operate under low-voltage low-power conditions, at microwave frequencies and/or in the temperature range 200-350 degreesC

Power-delay product minimization in high-performance 64-bit carry-select adders

This paper analyzes methods to minimize the power-delay product of 64-bit carry-select adders intended for high-performance and low-power applications. A first realization in 0.18-/spl mu/m partially depleted (PD) silicon-on-insulator (SOI), using complex branch-based logic (BBL) cells, results in a delay of 720 ps and a power dissipation of 96 mW at 1.5 V. The reduction of the stack height in the critical path, combined with the optimization of the global carry network with cell sharing and the selection of 8-bit pre-sums, leads to a reduction of the power-delay product by 75%. The automatic tuning of the transistor widths in 0.13-/spl mu/m PD SOI produces an energy-efficient 64-bit adder which has a delay of 326 ps and a power dissipation of 23 mW only at 1.1 V.

Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell

A full-adder implemented by combining branch-based logic and pass-gate logic is presented in this contribution. A comparison between this proposed full-adder (named BBL_PT) and its counterpart in conventional CMOS logic, was carried out in a 0.13mum PD (partially depleted) SOI CMOS for a supply voltage of 1.2V and a threshold voltage of 0.28V. Moreover, MTCMOS (multi-threshold) circuit technique was applied on the proposed full-adder to achieve a trade-off between Ultra-Low power and high performance design. Design with DTMOS (dynamic threshold) devices was also investigated with two threshold voltage values (0.28V and 0.4V) and V-dd = 0.6V.

Deep-submicrometer DC-to-RF SOI MOSFET macro-model

We present a submicrometer RF fully depleted SOI MOSFET macro-model based on a complete extrinsic small-signal equivalent circuit and an improved CAD model for the intrinsic device. The delay propagation effects in the channel are modeled by splitting the intrinsic transistor into a series of shorter transistors, for each of which a quasistatic device model can be used. Since the intrinsic device model is charge-based, our RF SOI MOSFET model can be used in both small and large-signal analyses. The model has been validated for frequencies up to 40 GHz and effective channel lengths down to 0.16 /spl mu/m.

Design of a branch-based 64-bit carry-select adder in 0.18 /spl mu/m partially depleted SOI CMOS

The paper presents the design of a 64-bit carry-select adder in Branch-Based Logic, a static design style that minimizes the internal node capacitances. This feature is used to lower the dynamic power dissipation, while maintaining good speed performances. The experimental realization of the adder demonstrates an overall delay of 720 ps while only dissipating 96 mW at 1 GHz. The fabrication is based on the 0.18 μm IBM CMOS8S2 SOI technology, which uses partially depleted transistors and copper metallization.

SOI technology for future high-performance smart cards

Chips based on silicon-on-insulator (SOI) technology meet the tough performance and security requirements presented by smart cards. A test chip manufactured in a fully depleted SOI process incorporates a charge pump and random-number generator, critical smart-card circuit blocks.

Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 µm Bulk and Silicon-On-Insulator CMOS Technologies

By reducing the parasitic node capacitances, the Branch-Based Logic design style can increase the performances of digital circuits. In order to benefit from the full potential of the design style and to be able to port it to different technologies, it is important to take into account the specific features of each technology. We investigate the case of three advanced 0.25 µm CMOS technologies: bulk, Partially-Depleted SOI and Fully-Depleted SOI. The design of a 16-bit carry-select Branch-Based adder IP is discussed. The Branch-Based adder shows lower power consumption compared to an implementation with conventional CMOS logic gates.