Imran Rafiq Quadri

Targeting reconfigurable FPGA based SoCs using the UML MARTE profile: from high abstraction levels to code generation

As SoC design complexity is escalating to new heights, there is a critical need to find adequate approaches and tools to handle SoC co-design aspects. Additionally, modern reconfigurable SoCs offer advantages over classical SoCs as they integrate adaptivity features to cope with mutable design requirements and environment needs. This paper presents a novel approach to address system adaptivity and reconfigurability. A generic model of reactive control is presented in a SoC codesign framework: Gaspard. Afterwards, control integration at different levels of the framework is illustrated for both functional specification and FPGA synthesis. The presented work is based on Model-Driven Engineering and the UML MARTE profile proposed by Object Management Group, for modeling and analysis of real-time embedded systems. The paper thus presents a complete design flow to move from high level MARTE models to code generation, for implementation of dynamically reconfigurable SoCs.

Expressing embedded systems configurations at high abstraction levels with UML MARTE profile: Advantages, limitations and alternatives

Embedded systems have become an essential aspect of our professional and personal lives. From avionics, transport and telecommunication systems to general commercial appliances such as smart phones, high definition TVs and gaming consoles; it is difficult to find a domain where these systems have not made their mark. Moreover, Systems-on-Chips (SoCs) which are considered as an integral solution for designing embedded systems, offer advantages such as run-time reconfiguration that can change system configurations during execution, depending upon Quality-of-Service (QoS) criteria such as performance and energy levels. This article deals with aspects related to modeling of these configurations, useful for describing various states of an embedded system, from both structural and operational viewpoints. Our proposal adapts a high abstraction level approach based on the principles of Model-Driven Engineering (MDE) and takes into account the UML MARTE profile for modeling of real-time and embedded systems. Elevating the design abstraction levels help to increase design productivity and achieve execution platform independence, among other advantages. The article details the current proposition of configurations in MARTE via some examples, and points out the advantages as well as some limitations, mainly concerning the semantic aspects of the defined concepts. Finally, we report our experiences on the modeling of an alternate notion of configurations and execution modes within the MARTE compliant Gaspard2 SoC Co-Design framework that has been successful for the design as well as implementation of FPGA based SoCs.

Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation

Due to continuous hardware/software evolution related to Systems-on-Chip (SoC) and the addition of features such as Partial Dynamic Reconfiguration, the complexity of SoC design and development has escalated exponentially. This has resulted in increased time to market and development costs. Without the usage of effective design tools and methodologies, large complex SoCs are becoming increasingly difficult to manage, resulting in a productivity gap. The design space, representing all technical decisions that need to be elaborated by the SoC design team is therefore, becoming immense and difficult to explore. Similarly, manipulation of these systems at low implementation levels such as Register Transfer Level (RTL) can be hindered by human interventions and the subsequent errors. This paper presents a novel design methodology that decreases the design complexity by raising the design abstraction levels. It makes use of Model-Driven Engineering and the UML MARTE profile to move from high level UML models to automatic code generation, for implementing dynamically reconfigurable SoCs.

High level modeling of dynamic reconfigurable FPGAs

As System-on-Chip (SoC) based embedded systems have become a defacto industry standard, their overall design complexity has increased exponentially in recent years, necessitating the introduction of new seamless methodologies and tools to handle the SoC codesign aspects. This paper presents a novel SoC co-design methodology based on Model Driven Engineering and the Modeling and Analysis of Real-Time and Embedded Systems (MARTE) standard, permitting us to raise the abstraction levels and allows to model fine grain reconfigurable architectures such as FPGAs. Extensions of this methodology have enabled us to integrate new features such as Partial Dynamic Reconfiguration supported by Modern FPGAs. The overall objective is to carry out system modeling at a high abstraction level expressed in a graphical language like Unified Modeling Language (UML) and afterwards transformation of these models automatically generate the necessary code for FPGA synthesis.

Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis

Reconfigurable FPGA based Systems-on-Chip (SoC)architectures are increasingly becoming the preferred solution for implementing modern embedded systems, due to their flexible nature. However due to the tremendous amount of hardware resources available in these systems, new design methodologies and tools are required to reduce their design complexity. In this paper we present an exploratory analysis for specification of these systems, while utilizing the UML MARTE (Modeling and Analysis of Real-time and Embedded Systems) profile. Our contributions permit us to model fine grain reconfigurable FPGA based SoC architectures while extending the profile to integrate new features such as Partial Dynamic Reconfiguration supported by these modern systems. Finally we present the current limitations of the MARTE profile and ask some open questions regarding how these high level models can be effectively used as input for commercial FPGA simulation and synthesis tools. Solutions to these questions can help in creating a design flow from high level models to synthesis, placement and execution of these reconfigurable SoCs.

Using an MDE Approach for Modeling of Interconnection Networks

As system-on-chip (SoCs) become more complex, high performance interconnection mediums are required to handle their complexity. Network-on-chips (NoCs) enable integration of more intellectual properties (IPs) into the SoC with increased performance. In the recent MARTE (modeling and analysis of real-time and embedded systems) profile, a notion of multidimensional multiplicity has been proposed to model repetitive structures and topologies. This paper presents a modeling methodology based on that notation to model the delta network family of interconnection networks for NoC construction.

MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs

As System-on-Chip (SoC) architectures become pivotal for designing embedded systems, the SoC design complexity continues to increase exponentially necessitating the need to find new design methodologies. In this paper we present a novel SoC co-design methodology based on Model Driven Engineering using the MARTE (Modeling and Analysis of Real-time and Embedded Systems) standard. This methodology is utilized to model fine grain reconfigurable architectures such as FPGAs and extends the standard to integrate new features such as Partial Dynamic Reconfiguration supported by modern FPGAs. The goal is to carry out modeling at a high abstraction level expressed in UML (Unified Modeling Language) and following transformations of these models, automatically generate the code necessary for FPGA implementation.

Models for Co-design of Heterogeneous Dynamically Reconfigurable SoCs

The design of Systems-on-Chip is becoming an increasing difficult challenge due to the continuous exponential evolution of the targeted complex architectures and applications. Thus, seamless methodologies and tools are required to resolve the SoC design issues. This chapter presents a high level component based approach for expressing system reconfigurability in SoC co-design. A generic model of reactive control is presented for Gaspard2, a SoC co-design framework. Control integration in different levels of the framework is explored along with a comparison of their advantages and disadvantages. Afterwards, control integration at another high abstraction level is investigated which proves to be more beneficial then the other alternatives. This integration allows to integrate reconfigurability features in modern SoCs. Finally a case study is presented for validation purposes. The presented works are based on Model-Driven Engineering (MDE) and UML MARTE profile for modeling and analysis of real-time embedded systems.

Model based design flow for implementing an anti-collision radar detection system

In order to ensure and increase the safety and reliability of transport systems, these systems are becoming more and more intelligent. They integrate more and more sensors and communication systems. Each of these functionalities can be implemented on a System-on-Chip (SoC). These functionalities are carried out by massive computations. As the number of integrated functionalities increase in the transport systems, the design and implementation complexity also increases at a tremendous rate. Implementation of these functionalities can be carried out either via FPGAs or DSP (digital signal processors) platforms. FPGAs are considered the ideal choice as they accelerate the computations by executing the algorithms in a parallel manner.