In-hyuk Choi

Induction of proinflammatory mediators requires activation of the TRAF, NIK, IKK and NF-κB signal transduction pathway in astrocytes infected with Escherichia coli

Escherichia coli is associated with inflammation in the brain. To investigate whether astrocytes are involved in E. coil‐induced inflammation, we assessed the levels of expression of proinflammatory mediators produced by E. coli‐infected astrocytes. E. coli infection in primary human astrocytes and cell lines increased expression of the CXC chemokine IL‐8/GRO‐α, the CC chemokine MCP‐1, TNF‐α, and iNOS. E. coli infection activated p65/p50 heterodimeric NF‐κB and concurrently decreased the signals of IκBα. Blocking the NF‐κB signals by IκBα‐superrepressor‐containing retrovirus or antisense p50 oligonucleotide transfection resulted in down‐regulation of expression of the proinflammatory mediators. Furthermore, superrepressors of IκBα, IκB kinase (IKK) or NF‐κB inducing kinase (NIK) inhibited the up‐regulated expression of the downstream target genes of NF‐κB such as IL‐8 and MCP‐1, and superrepressors of TNF receptor‐associated factor (TRAF)2 and TRAF5 also inhibited expression of the E. coli‐induced target genes of NF‐κB. These results indicate that proinflammatory mediators such as the CXC chemokine IL‐8/GRO‐α, the CC chemokine MCP‐1, TNF‐α, and iNOS can be expressed in E. coli‐infected astrocytes via an NF‐κB pathway, suggesting that these mediators may contribute to inflammation in the brain, including infiltration of inflammatory cells.

p38 Mitogen-activated protein kinase modulates expression of tumor necrosis factor-related apoptosis-inducing ligand induced by interferon-γ in fetal brain astrocytes

This study describes the involvement of the p38 mitogen‐activated protein kinase (MAPK) during interferon‐γ (IFN‐γ) signaling in fetal brain astrocytes. In some pathological conditions of brain, p38 MAPK transduces stress‐related signals, increases expression of proinflammatory cytokines, and induces cellular damage or apoptosis. In astrocytes, the tumor necrosis factor (TNF)‐related apoptosis‐inducing ligand (TRAIL) expression level was increased by IFN‐γ. AG490, a JAK inhibitor, blocked TRAIL expression induced by IFN‐γ. SB203580, a specific p38α and p38β2 MAPK inhibitor, decreased the TRAIL expression induced by IFN‐γ. The phosphorylation of the Ser727 site of STAT1, but not the Tyr701 site, was inhibited by SB203580. These results suggest that p38 MAPK modulates STAT1 phosphorylation in IFN‐γ signaling in fetal brain astrocytes.

Linearization of DFB laser diode by external light-injected cross-gain modulation for radio-over-fiber link

A novel linearization technique of distributed-feedback laser diode in analog optical transmitter for radio-over-fiber (RoF) link was proposed. The proposed scheme was based on a light-injection technique using cross-gain modulation effect. According to the proposed idea, a linearized RoF transmitter module was implemented and evaluated. The enhanced performance of carrier-to-noise ratio and spurious-free dynamic range were experimentally demonstrated in a wide range of radio-frequency (RF) applications. The experimental results show that the proposed scheme can be applicable for broadband RF optical transmission applications.

Overexpression of LIM Kinase 1 Renders Resistance to Apoptosis in PC12 Cells by Inhibition of Caspase Activation

LIM kinases (LIMKs) regulate actin polymerization by phosphorylating cofilin and are predominantly expressed in neural tissue. In this study, the effect of LIMK1 overexpression in PC12 cell apoptosis was investigated. PC12 cells overexpressing the wild-type LIMK1 were more resistant to serum-withdrawal-induced cell death and the level of caspase 3 activation in these cells was lower than in the control PC12 cells or than in the PC12 cells expressing a mutant LIMK1 lacking the kinase domain. The inhibition of JNK activation was observed in the PC12 cells overexpressing the wild-type LIMK1 after serum withdrawal. These results suggest that the LIMK1 might allow resistance to apoptosis in PC12 cells by inhibiting JNK activation.

A Scalable and Parallel Test Access Strategy for NoC-Based Multicore System

This paper proposes a new parallel test access strategy for multiple identical cores in a network-on-chip (NoC). The proposed test strategy takes advantage of the regular design of NoC to reduce both test area overhead and test time. The proposed NoC reused test access mechanism (TAM) adopted a pipelining structure and a deterministic test data routing algorithm in order to reuse the full bandwidth of links in the NoC. Also, the architecture has complete scalability according to the number of cores and applications for 3D environment are also represented. Experimental results show that the proposed TAM can test multiple cores with the same test time as a single core and negligible hardware overhead.

Estimation of the Groundwater Recharge Rate during a Rainy Season at a Headwater Catchment in Gwangneung, Korea

Groundwater recharge rates were estimated and compared in a headwater catchment at the Gwangneung Supersite using three different methods: water-table fluctuation (WTF), mass balance, and hydrograph separation techniques. Data were obtained during the rainy season from June to September 2005. Two different WTF methods estimated the groundwater recharge rate as 25.9% and 23.6%. The mass balance calculation of chloride ions indicated recharge rates of 13.4% on average. Baseflow separation using chloride ion as a tracer from six storm hydrographs produced a 14.0% net baseflow rate on average. Because of the implicit assumption of a long-term steady state without storage change, recharge rates calculated by mass balance and hydrograph separation were smaller than those done with WTF methods, which include the amount of increased storage due to the water-level rise. Subsequently, the WTF method is superior to others in the estimation of groundwater recharge rate to comprehend the dynamic characteristics of the hydrologic cycle.

Majority-Based Test Access Mechanism for Parallel Testing of Multiple Identical Cores

The increased use of multicore chips diminishes per-core complexity and also demands parallel design and test technologies. An especially important evolution of the multicore chip has been the use of multiple identical cores, providing a homogenous system with various merits. This paper introduces a novel test access mechanism (TAM) for parallel testing of multiple identical cores and identifying faulty cores to derate the chip by excluding it. Instead of typical test response data from the cores, the test output data used in this paper are the majority values, that is, the typical test responses from the cores. All the cores can thereby be tested in parallel and test costs (in both test pins and test time) are exactly the same as for a single core. The proposed TAM can be implemented with on-chip comparators and majority analyzers. The experimental results in this paper show that the proposed TAM can test multiple cores with minimal test pins and test time and with hardware overhead of <;0.1%.

DRAM-Based Error Detection Method to Reduce the Post-Silicon Debug Time for Multiple Identical Cores

In the post-silicon debug of multicore designs, the debug time has increased significantly because the number of cores undergoing debug has increased; however the resources available to debug the design are limited. This paper proposes a new DRAM-based error detection method to overcome this challenge. The proposed method requires only three debug sessions even if multiple cores are present. The first debug session is used to detect the error intervals of each core using golden signatures. The second session is used to detect the error clock cycles in each core using a golden data stream. Instead of storing all of the golden data, the golden data stream is generated by selecting error-free debug data for each interval which are guaranteed by the first session. Finally, the error data in all cores are only captured during the third session. The experimental results on various debug cases show significant reductions in total debug time and the amount of DRAM usage compared to previous methods.

An On-Chip Error Detection Method to Reduce the Post-Silicon Debug Time

Debug time has become a major issue in post silicon debug because of the increasingly complicated nature of circuit design. However, reducing debug time is a major challenge because of the limited size of the trace buffer used to observe internal signals in the circuit. This study proposes an on-chip error detection method to overcome this challenge. The on-chip process detects the error-suspect window using the pre-calculated golden data stored in the trace buffer. This allows the selective compaction and capture of the debug data in the trace buffer during the error-containing interval. As a result, reducing the number of debug sessions significantly reduces the total debug time. The experimental results on various debug cases show significant reductions in total debug time compared to previous work.

A TSV test structure for simultaneously detecting resistive open and bridge defects in 3D-ICs

After the 3D stacking process, TSV-based 3D-ICs are required to perform the post-bond testing in order to detect TSV faults or device functional defects. To detect the resistive open and bridge defects, various effective TSV testing techniques have been studied. At an early stage of TSV manufacturing, it is important to consider that the TSV testing is required not only determining whether each TSV is defective or non-defective, but also digitizing the fault degree into the TSV resistance value during the silicon debugging. In this paper, we propose a new TSV test structure for simultaneously detecting the resistive open and bridge defects with supporting the debug mode to analysis the characteristic of the specific TSV. It can highly reduce the test time by detecting TSV defects at the same time without compromising test quality.