Taewoo Han

An Advanced BIRA for Memories With an Optimal Repair Rate and Fast Analysis Speed by Using a Branch Analyzer

As memory capacity and density grow, a corresponding increase in the number of defects decreases the yield and quality of embedded memories for systems-on-chip as well as commodity memories. For embedded memories, built-in redundancy analysis (BIRA) is widely used to solve quality and yield issues by replacing faulty cells with healthy redundant cells. Many BIRA approaches require extra hardware overhead in order to achieve optimal repair rates, or they suffer a loss of repair rate in minimizing the hardware overhead. An innovative BIRA approach is proposed to achieve optimal repair rates, lower area overhead, and increase analysis speed. The proposed BIRA minimizes area overhead by eliminating some storage coverage for only must-repair faulty information. The proposed BIRA analyzes redundancies quickly and efficiently by evaluating all nodes of a branch in parallel with a new analyzer which is simple and easy-to-implement. Experimental results show that the proposed BIRA allows for a much faster analysis speed than that of the state-of-the-art BIRA, as well as the optimal repair rate, and relatively small area overhead.

A Scalable and Parallel Test Access Strategy for NoC-Based Multicore System

This paper proposes a new parallel test access strategy for multiple identical cores in a network-on-chip (NoC). The proposed test strategy takes advantage of the regular design of NoC to reduce both test area overhead and test time. The proposed NoC reused test access mechanism (TAM) adopted a pipelining structure and a deterministic test data routing algorithm in order to reuse the full bandwidth of links in the NoC. Also, the architecture has complete scalability according to the number of cores and applications for 3D environment are also represented. Experimental results show that the proposed TAM can test multiple cores with the same test time as a single core and negligible hardware overhead.

An Advanced BIRA using parallel sub-analyzers for embedded memories

Although many built-in redundancy analysis (BIRA) algorithms which use parallel sub-analyzers have optimal repair rate and a fast analysis speed, they suffer from a large area overhead. To reduce the area overhead, a new BIRA analyzer is proposed which reconstructs the content addressable memory (CAM) structure of the parallel sub-analyzers like a binary searching tree. Experimental results show that the proposed BIRA analyzer achieves 25% reduction of area overhead compared with previous BIRA using parallel sub-analyzers in case an embedded memory has 4 spares with optimal repair rate and zero analysis speed.

Majority-Based Test Access Mechanism for Parallel Testing of Multiple Identical Cores

The increased use of multicore chips diminishes per-core complexity and also demands parallel design and test technologies. An especially important evolution of the multicore chip has been the use of multiple identical cores, providing a homogenous system with various merits. This paper introduces a novel test access mechanism (TAM) for parallel testing of multiple identical cores and identifying faulty cores to derate the chip by excluding it. Instead of typical test response data from the cores, the test output data used in this paper are the majority values, that is, the typical test responses from the cores. All the cores can thereby be tested in parallel and test costs (in both test pins and test time) are exactly the same as for a single core. The proposed TAM can be implemented with on-chip comparators and majority analyzers. The experimental results in this paper show that the proposed TAM can test multiple cores with minimal test pins and test time and with hardware overhead of <;0.1%.

An online test and debug methodology for automotive image processing system

In the digital system where safety is a major issue, the reliability issue has been more important. However, as the circuit design has been more complicated, the number of some errors which escaped from the pre-silicon verification has been increased and the undetected errors have a bad influence upon reliability. To solve this problem, an online test and debug methodology for the automotive image processing system is proposed in this paper. Experimental results show the proposed methodology has high system reliability and provides the concurrent operation with a negligible test time and a small hardware overhead compared to the previous works.

A novel test access mechanism for parallel testing of multi-core system

The increased usages of multi-core systems diminish percore complexity and also demand several parallel design and test technologies. This paper introduces a novel test access mechanism (TAM) for parallel testing of multiple identical cores. Instead of typical test response data from the cores, the test output data used in this paper are the majority values extracted from the typical test response from the cores. All the cores can be tested in parallel and test costs (test time, test pins) are exactly the same as for a single core. The experiment results in this paper show the proposed TAM can test multiple cores with minimal test pins and test time and with negligible hardware overhead.

Test Scheduling Using Ant Colony Optimization for 3D Integrated Circuits

Cost of test scheduling for the 3D integrated circuits (IC) test is increased compared to the 2D IC due to the constraint factors such as the width of Test Access Mechanism (TAM), the number of Through Silicon Via (TSVs), thermal constraint, and test pin count constraint. In this paper, a low cost test scheduling mechanism using Ant Colony Algorithm (ACO) for the 3D IC is proposed. The experimental results using simulation demonstrate that the proposed algorithm has an effective solution for the 3D IC test scheduling.

Bit transmission error correction scheme for FlexRay based automotive communication systems

In the FlexRay communication network systems which are configured as a large number of ECUs (Electronic Control Units) and network topologies, the receivers have the different asymmetric transmission delays which cause the transmission errors. As the complexity of the communication network topology in vehicle increases, the asymmetric delay is getting longer. In this paper, the error estimation and correction scheme to ensure the integrity of the signal during operation when the transmission error occurs due to the asymmetric delay is proposed. Simulation results show the proposed scheme can correct the transmission errors effectively in performance.

Path search engine for fast optimal path search using efficient hardware architecture

Recently, the optimal path search based on real-time traffic information is becoming more important in car navigation industries. The preference-based Ant Colony Optimization algorithm is suitable for the path search in a real-time traffic circumstance. However, this algorithm is not applicable to current car navigation due to the slow search time caused by the complex calculations. Likewise, sub-optimal problem is occurred according to circumstances of probability-based search and parameter settings in this algorithm. This paper presents a path search engine for the fast optimal path search, using simplified calculation and parallel architectures to apply path search algorithm. Also, A∗ architecture is added in the path search engine to supplement sub-optimal problem. The path search engine obtains the accurate optimal path and the search time improvement compared to the software-based path search in a general purpose processor that is typically used for car navigation.