Hyunggoy Oh

A Scalable and Parallel Test Access Strategy for NoC-Based Multicore System

This paper proposes a new parallel test access strategy for multiple identical cores in a network-on-chip (NoC). The proposed test strategy takes advantage of the regular design of NoC to reduce both test area overhead and test time. The proposed NoC reused test access mechanism (TAM) adopted a pipelining structure and a deterministic test data routing algorithm in order to reuse the full bandwidth of links in the NoC. Also, the architecture has complete scalability according to the number of cores and applications for 3D environment are also represented. Experimental results show that the proposed TAM can test multiple cores with the same test time as a single core and negligible hardware overhead.

DRAM-Based Error Detection Method to Reduce the Post-Silicon Debug Time for Multiple Identical Cores

In the post-silicon debug of multicore designs, the debug time has increased significantly because the number of cores undergoing debug has increased; however the resources available to debug the design are limited. This paper proposes a new DRAM-based error detection method to overcome this challenge. The proposed method requires only three debug sessions even if multiple cores are present. The first debug session is used to detect the error intervals of each core using golden signatures. The second session is used to detect the error clock cycles in each core using a golden data stream. Instead of storing all of the golden data, the golden data stream is generated by selecting error-free debug data for each interval which are guaranteed by the first session. Finally, the error data in all cores are only captured during the third session. The experimental results on various debug cases show significant reductions in total debug time and the amount of DRAM usage compared to previous methods.

An On-Chip Error Detection Method to Reduce the Post-Silicon Debug Time

Debug time has become a major issue in post silicon debug because of the increasingly complicated nature of circuit design. However, reducing debug time is a major challenge because of the limited size of the trace buffer used to observe internal signals in the circuit. This study proposes an on-chip error detection method to overcome this challenge. The on-chip process detects the error-suspect window using the pre-calculated golden data stored in the trace buffer. This allows the selective compaction and capture of the debug data in the trace buffer during the error-containing interval. As a result, reducing the number of debug sessions significantly reduces the total debug time. The experimental results on various debug cases show significant reductions in total debug time compared to previous work.

A 2-D compaction method using macro block for post-silicon validation

The post-silicon validation has been an important step as the complexity of system on chip (SoC) increases. Conventional trace buffer based debug methods offer consecutive observability and real time debug, but the size constraint of the trace buffer still is a challenge. The proposed method uses 2-D compaction for expanding the depth of observation window in a trace buffer. Moreover, the macro block, which is used with 2-D compaction, offers tolerance to various error patterns as a virtual window. The errors identified by the 2-D compaction using the macro block are selectively captured by using the new tag map. The experimental results show that the proposed method enables the reduction of error misidentification.

An online test and debug methodology for automotive image processing system

In the digital system where safety is a major issue, the reliability issue has been more important. However, as the circuit design has been more complicated, the number of some errors which escaped from the pre-silicon verification has been increased and the undetected errors have a bad influence upon reliability. To solve this problem, an online test and debug methodology for the automotive image processing system is proposed in this paper. Experimental results show the proposed methodology has high system reliability and provides the concurrent operation with a negligible test time and a small hardware overhead compared to the previous works.

A debug scheme to improve the error identification in post-silicon validation

While developing semiconductors, post-silicon validation is an important step to identify the errors that are not detected during the pre-silicon verification and manufacturing testing phases. When the design complexity increases, the required debug time also increases because additional debug data are required to identify the errors. In this study, we present a debug scheme that improves the error identification capability. The proposed debug approach concurrently generates three types of signatures using hierarchical multiple-input signature registers (MISRs). The error-suspect debug cycles are determined by analyzing the debug cycles that are commonly contained in the erroneous signatures of the three MISRs. To reduce the amount of debug data, we compare the high-level MISR signatures in real time with the golden signatures; further, we handle the remaining two MISRs based on the tag bits that are obtained from the results of the high-level MISR. The experimental results prove that the proposed debug structure can significantly improve the error identification capability using less debug data than that used in previous debug structure.

Thermal Aware Test Scheduling for NTV Circuit

Although the near threshold voltage (NTV) design has achieved energy efficiency, certain challenges remain regarding its application. In this paper, we describe the analysis of thermally induced reliability concern in test process. In an NTV environment, the thermal dependency of a circuit delay is changed, and a difference in thermal constraints from that in a nominal voltage design exists. In addition, we propose a new test scheduling method for NTV circuits that alleviates the thermal constraints in system-on-chip test processes. Our simulation results show that the test time could be reduced while minimizing the reliability loss.

Reconfigurable scan architecture for Test Power and Data Volume Reduction

With exponential development in the semiconductor technology in recent years, the magnitudes of test power consumption and test data volumes have increased significantly. This has resulted in over-testing because of IR drops. This paper proposes a reconfigurable scan architecture to overcome these challenges. The proposed architecture increases the flexibility of the scan partitioning technique to maximize the reduction in the switching activity, and it uses the scan segment skip technique to reduce the data volume. The results show that our method is able to achieve significant reductions in the total test power and data volumes compared with previous methods.

A novel X-filling method for capture power reduction

This paper proposes a X-filling method that reduces capture power during scan-based testing. The proposed method classifies scan cells for dividing the scan cells into some groups. Then, based on the divided groups, X-bits are filled simultaneously to reduce the computation time. Since the proposed method uses a novel grouping algorithm and fills X-bits based on groups, the proposed method reduces switching activity and computation time when compared with conventional X-filling methods. The simulation results show that the proposed method reduces the switching activity up to 70% and the number of simulations for the X-filling up to 52% compared with that of conventional X-filling methods.

Process variation-aware bridge fault analysis

Bridge faults are important that cause a reliability concern. Since process variation affects the bridge faults, it should be considered for bridge fault analysis. This paper proposes a new analysis method for resistive bridge faults considering process variation. The proposed method analyzes defect coverage for resistive bridge faults by using circuit level modeling. The proposed method uses the lower level analysis and it reduces redundant test patterns for bridge test.