In-kyun Shin

Minimization of line edge roughness and critical dimension error in electron-beam lithography

As the minimum feature size continues to decrease, the line edge roughness (LER) has become a critical issue to be addressed. The LER is caused by a number of stochastically fluctuating effects involved in the fabrication process using electron-beam lithography. Since the LER does not scale with the feature size, it can significantly limit the minimum feature size and the maximum circuit density that can be achieved in a pattern of nanoscale features. Many of the efforts to decrease the LER in the past took an empirical or trial-and-error approach. In this study, a computational approach is taken in developing effective methods to minimize the LER, taking the critical dimension (CD) error due to the proximity effect also into account. Since the LER and the CD error vary with the resist-depth dimension, a 3D model is employed instead of a 2D model used in most of the previous work. The simulation results show that the proposed methods have potential to provide a practical and effective way to minimize the LER.

Determination and analysis of minimum dose for achieving vertical sidewall in electron-beam lithography

Prior to carrying out the proximity effect correction by optimizing the spatial distribution of dose in electron beam lithography, one first needs to determine the minimum total dose required. A conventional method typically used to determine the minimum total dose is the trial-and-error approach, which can be unnecessarily costly and wasteful. In this paper, two new dose determination methods are described, which utilize the concept of a “critical path” without any proximity effect correction effort. Also, the dependency of the minimum total dose and dose distribution on the feature and lithographic parameters is investigated. The simulation results show that the proposed dose-determination methods can adaptively and efficiently determine the minimum total dose. Thus, they have the potential to provide a practical and effective alternative to the conventional trial-and-error approach.

Derivation of line edge roughness based on analytic model of stochastic exposure distribution

As the feature size is reduced well below 100 nm, the line edge roughness (LER) becomes a critical issue since it does not scale with feature size. For minimizing the LER, it is essential to be able to accurately estimate it. A possible method for LER estimation is to rely on simulation. However, it requires time-consuming procedures, i.e., the Monte Carlo simulation for computing the exposure distribution within resist, and a resist-development simulation. In this study, an analytic method for estimating the LER, defined as the standard deviation of edge location, is developed to overcome the drawback of simulation method. This new approach first relates the stochastic exposure to the statistics of point spread functions, i.e., mean and variance, and eventually derives the variation of edge location considering critical paths in the resist development process. The analytic method achieves good accuracy compared to a simulation method and has a good potential to be employed in practice.

Effect of SPM-based cleaning POR on EUV mask performance

EUV masks include many different layers of various materials rarely used in optical masks, and each layer of material has a particular role in enhancing the performance of EUV lithography. Therefore, it is crucial to understand how the mask quality and patterning performance can change during mask fabrication, EUV exposure, maintenance cleaning, shipping, or storage. The fact that a pellicle is not used to protect the mask surface in EUV lithography suggests that EUV masks may have to undergo more cleaning cycles during their lifetime. More frequent cleaning, combined with the adoption of new materials for EUV masks, necessitates that mask manufacturers closely examine the performance change of EUV masks during cleaning process. We have investigated EUV mask quality and patterning performance during 30 cycles of Samsungs EUV mask SPM-based cleaning and 20 cycles of SEMATECH ADT exposure. We have observed that the quality and patterning performance of EUV masks does not significantly change during these processes except mask pattern CD change. To resolve this issue, we have developed an acid-free cleaning POR and substantially improved EUV mask film loss compared to the SPM-based cleaning POR.

Experimental verification of achieving vertical sidewalls for nanoscale features in electron-beam lithography

It is often necessary to achieve a vertical sidewall in the remaining resist profile obtained through electron-beam lithographic process. For nanoscale features, the spatial dose distribution of V-shape typically used in a conventional two-dimensional proximity effect correction scheme cannot easily achieve a vertical sidewall while also minimizing the critical dimension (CD) error. In an earlier study, it was shown through simulation based on a three-dimensional model that new types of spatial dose distributions, i.e., M- and A-shapes, are effective in achieving vertical sidewalls and minimizing the CD error and total dose. These two dose distributions exploit the fact that the exposure varies along the depth dimension with high and low contrasts at the top and bottom layers of resist, respectively. In this study, a number of experiments have been carried out in order to verify the simulation results reported earlier. This paper includes a review of the new dose distribution types and experimental results with a detailed discussion.

EUVL mask inspection using 193nm wavelength for 30nm node and beyond

We report inspection results of EUVL masks with 193nm wavelength tools for 30nm and 24nm half-pitch nodes. The dense line and space and contact pattern is considered to study inspection capability. The evaluation includes defect contrast variation depending on illumination conditions, defect types, and design nodes. We show many inspection images with various optic conditions. Consequently, the detection sensitivity is affected by contrast variation of defects. The detection sensitivity and wafer printability are addressed with a programmed defect mask and a production mask. With these results, we want to discuss the capability of current EUVL mask inspection tools and the future direction.

Practical approach to modeling e-beam lithographic process from SEM images for minimization of line edge roughness and critical dimension error

Two main factors which limit the minimum feature size and the maximum circuit density achievable by electron-beam (e-beam) lithography are the line edge roughness (LER) and the proximity effect. Since the LER is caused by the stochastic nature of the exposing and development processes, it does not scale with the feature size. Therefore, reducing the LER is essential as the feature size continues to decrease. Accurate modeling of the LER and the proximity effect analytically or via simulation for their minimization is either difficult or costly in many cases. In this study, a practical method for extracting the essential information from SEM images, needed to characterize the e-beam lithographic process, and an effective method for minimizing the LER and critical dimension error based on the extracted information have been developed. The main objective is that the methods utilize only the information extracted from SEM images without having to know the complete setup of e-beam lithographic process. It has ...

Analytic estimation and minimization of line edge roughness in electron-beam lithography

As the feature size is reduced well below 100 nm, the line edge roughness (LER) will eventually become a resolution-limiting factor in the electron-beam (e-beam) lithography since the LER does not scale with the feature size. Therefore, it is essential to minimize the LER in order to achieve the highest resolution possible by the e-beam lithographic process. A simulation or experiment based method for minimizing the LER can be very time-consuming and expensive since repetitive simulations or experiments may be required. In this study, a new analytic model and a method for estimating the LER are developed based on the model, and an analytic procedure for minimizing the LER is also derived based on the new analytic model. In this new approach, the LER is derived from the distribution of the stochastic developing rate in the resist, which is assumed to be known. The results obtained by the analytic estimation method and the minimization procedure are shown to be close to those by the simulation method. The c...

Feasibility evaluations of alternating phase-shift mask for imaging sub-80nm feature with KrF

Alternating phase shift mask (AltPSM) is considered as one of the most promising technique in leading-edge lithography. Its optical performance can be verified by sub-100nm gate generation and guaranteed device properties, indicated as depth of focus (DOF) and on chip CD variation (OCV). Nevertheless, continuous gate reduction in logic device demands more high-qualified mask process and optimization of illumination to overcome resolution limit. As one of the solution, appropriate mask structure and OPC rule dependent on illumination condition are evaluated. Issues out of mask manufacturing and Cr-less PEPSM as substitution of PEPSM are also discussed. Besides, interrelation between issues of mask and optical characteristics are investigated and compared mutually. In the end of this paper, we propose the optimum mask type and opportune time for ArF lithography.

Application of Cr-less mask technology for sub-100nm gate with single exposure

Chrome Less phase lithography (CPL) may be the crucial technology to print 100nm node and below. CPL can apply to various design layers without causing phase conflicts, while phase edge phase shift mask (PEPSM) is beneficial for specific pattern configurations and pitches. Therefore, we tested the feasibility of CPL including phase grating and hybrid CPL. And we tested the two types of CPL such as mesa and trench structures to decide the proper shifter forming method. We evaluated pattern fidelity of CPL using simulation, aerial image measurement system (AIMS) and wafer printing. Finally, we will compare the optical performance between CPL and PEPSM for 100nm node SRAM gate.