Jin Choi

Mask writing time explosion and its effect on CD control in e-beam lithography

As semiconductor features shrink in size and pitch, the extreme control of CD uniformity and MTT is needed for mask fabrication with e-beam lithography. And because of huge shot density of data, the writing time of e-beam lithography for mask fabrication will be increased rapidly in future design node. The beam drift caused by charging of optic system and current density drift can affect the beam size, position and exposure dose stability. From the empirical data, those are the function of writing time. Although e-beam lithography tool has the correction function which can be applied during writing, there are remained errors after correction which result in CD uniformity error. According to the writing time increasing, the residual error of correction will be more important and give the limit of CD uniformity and MTT. In this study, we study the beam size and exposure dose error as a function of time. Those are mainly caused by charging and current density drift. And we present the predicted writing time of e-beam lithography below 32nm node and estimate its effect on CD control error. From the relation between writing time and CD control error, we achieve the limit of CD uniformity with e-beam mask writer. And we suggest the method to achieve required CD uniformity at 22nm node and beyond.

The requirements for the future e-beam mask writer: statistical analysis of pattern accuracy

As semiconductor features shrink in size and pitch, the extreme control of CD uniformity, MTT and image placement is needed for mask fabrication with e-beam lithography. Among the many sources of CD and image placement error, the error resulting from e-beam mask writer becomes more important than before. CD and positioning error by e-beam mask writer is mainly related to the imperfection of e-beam deflection accuracy in optic system and the charging and contamination of column. To avoid these errors, the e-beam mask writer should be designed taking into account for these effects. However, the writing speed is considered for machine design with the highest priority, because the e-beam shot count is increased rapidly due to design shrink and aggressive OPC. The increment of shot count can make the pattern shift problem due to statistical issue resulting from e-beam deflection error and the total shot count in layout. And it affects the quality of CD and image placement too. In this report, the statistical approach on CD and image placement error caused by e-beam shot position error is presented. It is estimated for various writing conditions including the intrinsic e-beam positioning error of VSB writer. From the simulation study, the required e-beam shot position accuracy to avoid pattern shift problem in 22nm node and beyond is estimated taking into account for total shot count. And the required local CD uniformity is calculated for various e-beam writing conditions. The image placement error is also simulated for various conditions including e-beam writing field position error. Consequently, the requirements for the future e-beam mask writer and the writing conditions are discussed. And in terms of e-beam shot noise, LER caused by exposure dose and shot position error is studied for future e-beam mask writing for 22nm node and beyond.

E-beam shot count estimation at 32 nm HP and beyond

Recent Low k1 era requires aggressive OPC technology with advanced lithography technology. The aggressive OPC contains the rounded pattern and a lot of assistant pattern which are the main source to increase the shot division. We have defined the shot complexity, which is defined by the ratio of number of shot between the interested pattern and the 1:1 L/S pattern. Based on shot complexity parameter, we have estimated the writing time as the device node decreases. We expect that the aggressive OPC and the high dose could generate severely the writing time issue in 32nm node era.

Image placement error of photomask due to pattern loading effect: analysis and correction technique for sub-45 nm node

As semiconductor features shrink in size and pitch, the image placement error at photomask has been interested as an important factor to be reduced. Especially, by the development of double exposure technique (DET) or double patterning technique (DPT) for sub-45 nm node the image placement error is required to be controlled tightly. Following ITRS roadmap, when DET or DPT is used the registration for sub-45 nm node is required to be less than 4 nm but this specification still corresponds to the challengeable goal. Among various sources of image placement errors, here, we focus on the error occurring at patterning process of photomask and discuss its effect on the photomask overlay. We name the image placement error occurred at patterning process due to e-beam charging effect, absorber etching effect, and so on as the pattern loading effect. We quantify the amount of pattern loading effect on registration error, analyze it with the help of simulation and experiment, and discuss the character of each error and correction method.

Degradation of pattern quality due to strong electron scattering in EUV mask

The ray tracing of electron based on Monte Carlo is simulated by GEANT software to investigate the electron scattering property in ArF photomask and EUV photomask. By Monte Carlo simulation, we have presented the mechanism of electron scattering in EUV photomask and simulated the electron distribution which gives rise to change the patterning performance of EUV photomask, compared with those of ArF photomask. Furthermore, the overlay error of EUV photomask has been analyzed by the charging model. EUV photomask has the additional electron distribution in the range of 2um, which comes from the strong electron scattering at Mo/Si multilayer. Because of this additional electron distribution, EUV photomask has the pattern size error due to proximity effect of electron when the conventional Gaussian function is used to correct the proximity effect of ArF photomask. The maximum residual error due to the proximity effect in EUV photomask is 7nm. Furthermore, we have confirmed that the linearity of pattern size is so different from ArF photomask and it is well explained with the Gaussian blur model based on the electron distribution of EUV photomask.

Pattern placement error due to resist charging effect at 50kV e-beam writer: mechanism and its correction

By the development of double exposure technique and the EUV lithography the pattern placement error of photomask is interested because of its impact on size and position of wafer pattern. Among various sources to induce the pattern placement error, we have focused on the resist charging effect and shown that the resist charging effect generates pattern position error and CD variation. Based on experiment and simulation, we present quantitatively the dependence of position error on pattern density, pattern shape, and writing order. Furthermore, we have discussed the model to describe the charging effect and its agreement with experiment, and correction method to remove the resist charging effect.

Requirements of e-beam size and position accuracy for photomask of sub-32 nm HP device

As semiconductor features shrink in size and pitch, there are strong needs for an advanced mask writer which has better patterning quality. Among various requirements for next photomask writer, we have focused on the requirements of ebeam size and position accuracy for hp 32nm and beyond generation. At the era of DPT, EUV, and complex OPC, the photomask is required to have extreme control of critical dimension (CD). Based on simulation and experiment, we present the e-beam requirements for advanced mask writer, in view point of stability and accuracy. In detail, the control of e-beam size in mask writer should be decreased to 0.5nm because the size error of e-beam gives rise to large CD error according to the high complexity of mask pattern. Furthermore, the drift error of beam position should be smaller than 1nm to obtain the tight pattern placement error and to minimize the edge roughness of mask pattern for the era of computational lithography and EUV lithography.

Requirements of photomask registration for the 45nm node and beyond : is it possible?

As semiconductor features shrink in size and pitch, the pattern placement error at photomask, that is, the registration becomes more important factor to be reduced. Following ITRS roadmap, the registration for sub-45 nm node is required to be less than 5 nm but this specification still corresponds to the challengeable goal. Among several reasons to induce registration, here, we have focused on four major registration errors: e-beam positioning error, patterning effect, pellicle attachment effect, and sampling error of measurement. We quantify and analyze each error with the help of finite element modeling and by experiment. Based on these results, we present the current status and the goal of each error for the roadmap of sub-45 nm node.