In-Yong Song

Synthesis of Multilayer Graphene Balls by Carbon Segregation from Nickel Nanoparticles

Three-dimensional (3D) structured graphene is a material of great interest due to its diverse applications in electronics, catalytic electrodes, and sensors. However, the preparation of 3D structured graphene is still challenging. Here, we report the fabrication of multilayer graphene balls (GBs) by template-directed carbon segregation using nickel nanoparticles (Ni-NPs) as template materials. To maintain the ball shape of the template Ni-NPs, we used a carburization process using polyol solution as the carbon source and a thermal annealing process to synthesize graphene layers via carbon segregation on the outer surface of the Ni-NPs. The resulting GBs were hollow structures composed of multilayer graphene after the removal of core Ni-NPs, and the thickness of the graphene layers and the size of GBs were tunable by controlling the graphene synthesis conditions. X-ray diffraction analysis and in situ transmission electron microscope characterization revealed that carbon atoms diffused effectively into the Ni-NPs during the carburization step, and that the diffused carbon atoms in Ni-NPs segregated and successfully formed a graphene layer on the surface of the Ni-NPs during thermal annealing. We also performed further heat treatment at high temperature to improve the quality of the graphene layer, resulting in highly crystalline GBs. The unique hollow GBs synthesized here will be useful as excellent high-rate electrode materials for electrochemical lithium storage devices.

Pd-nanocrystal-based nonvolatile memory structures with asymmetric SiO2∕HfO2 tunnel barrier

Pd nanocrystals (NCs) on asymmetric tunnel barrier (ATB) composed of stacked SiO2 and HfO2 layers have been employed for nonvolatile memory devices. The Pd-NC layers are formed by electrostatic self-assembly of negatively charged colloidal Pd NCs. The presence of isolated Pd NCs of ∼5nm embedded in HfO2 is confirmed by scanning and transmission electron microscopy images. Outstanding program∕erase (P∕E) properties from C‐V curves are observed with a memory window of 6V under ±17V. Extrapolation of the data up to ten years shows that the flatband voltage drops at the P∕E levels are maintained within only 1.0∕0.5V, respectively, resulting from the efficient data retention based on the ATB. These results are promising enough for the memory structure to be utilized for the multilevel charge storage.

Local modification of the thin YBa2Cu3O7−y microstrips by the voltage-biased atomic force microscope tip

The atomic force microscope (AFM) tip biased at around −15 V is found to be capable of locally modifying the entire thickness of 40-nm-thick semiconducting or superconducting YBa2Cu3O7−y microstrips in air. We show, using combined electrical and AFM measurements, that the local regions underneath the surface of the semiconducting or superconducting YBa2Cu3O7−y microstrips are transformed into either nonconducting or nonsuperconducting regions, respectively, upon applying the negatively biased AFM tip. The conductance of the nonsuperconducting regions is also found to be comparable to that of the superconducting regions before modification at 298 K.

Fabrication and characterization of electrically tunable high-Tc superconducting resonators incorporating barium strontium titanate as a tuning material

We have made the electrically tunable microstrip resonators by using both high-Tc superconducting and dielectric films. The two-pole resonators employ a dielectric barium strontium titanate film on their centre in the form of flip chip. The superconducting YBa2Cu3Oy (YBCO) and dielectric Ba0.1Sr0.9TiO3 were deposited on the CeO2-buffered sapphire substrate and LaAlO3 substrate, respectively, by a pulsed laser deposition technique. Variations of the relative permittivity, r, and dielectric loss tangent, tan, of the Ba0.1Sr0.9TiO3 were studied as a function of the applied dc bias at liquid-nitrogen temperature. The tunability, defined as C(0 V)/C(100 V), and loss tangent of the resonators were measured to be ~1.9 and 1.5 × 10-2 (at 100 V), respectively.

High-Tc edge junctions with a Ga-doped YBa2Cu3O7−δ barrier and interface resistances

High-Tc ramp-edge junctions with a Ga-doped YBa2Cu3O7−δ barrier have been fabricated in the trilayer geometry of YBa2Cu3O7−δ/YBa2Cu2.79Ga0.21O7−δ/YBa2Cu3O7−δ on LaAlO3 single crystals. Interface resistances of the junctions were drastically reduced by using an in situ Ar plasma cleaning treatment. The Ga-doped YBa2Cu3O7−δ junctions with barrier thickness of 200 and 300 A clearly exhibited resistively-shunted-junction-like current–voltage characteristics. The critical currents of the Ga-doped junctions were less sensitive to the variation of the barrier thickness compared to those of the other junctions. The increase of the barrier resistivity by Ga-doping and the in situ rf plasma cleaning treatment resulted in an enhancement of the junction reliability and reproducibility.

Preparation of Pd Nanocrystals onto Trenched Silicon Devices Confirmed by Electron Tomography

Monolayer arrays of monodispersed nanocrystals (<10 nm) onto three-dimensional substrates have considerable potential for various engineering applications due to their highly integrated features with nanocrystal homogeneity. Here we address the feasibility of arraying nanocrystal monolayers in wafer-scale onto three-dimensional substrates. We present nanocrystal Pd metal arrayed in monolayers onto trenched silicon wafers (4 in. diam) using a facile electrostatic adsorption scheme. We also present three-dimensional electron tomography bright-field projection images, which reveal that the resulting arrays of Pd nanocrystals indeed have the monolayer nature on the overall trenched wafer surface and are not affected by trench geometry.

Capacitive coupling model and extraction of the molecular interface states in porphyrin-silicon nanowire hybrid field-effect transistor

We modeled and extracted the distribution of interface trap density by grafted molecules on the surface of a silicon nanowire field-effect transistor (SNWFET). The subthreshold current model was employed, and the capacitive coupling model of ideality factor was simplified, using a fully depleted SNWFET. We applied the analytical model to p-channel SNWFET with porphyrin, and extracted the distribution of the molecular interface states. There were 748 and 474 traps (average value) in length (L) = 300 nm and L = 500 nm devices, respectively. The trap energy was in the range of 0.27–0.35 eV.

High-Tc ramp-edge junctions and dc SQUIDs with a Ga-doped YBCO barrier

We report on high-Tc ramp-edge junctions and dc superconducting quantum interference devices (SQUIDs) with a Ga-doped YBCO barrier. The interface resistances of the junctions were drastically reduced by in situ RF plasma cleaning treatment. The plasma gas and pressure were Ar, O2 and 50-100 mTorr, respectively. The lattice images of the interface of the junctions were analysed by high-resolution transmission electron microscopy. The effects of RF plasma treatment and barrier layer material on the junction properties were systematically investigated. These junctions were fabricated uniformly and reproducibly, and they displayed clear RSJ-like I-V characteristics with high values of IcRn products at 65 K. Dc SQUIDs fabricated with the Ga-doped YBCO junctions exhibited excellent voltage modulations in response to applied fields at 65 K.