Jong-Bong Park

Electrical manipulation of nanofilaments in transition-metal oxides for resistance-based memory.

The fabrication of controlled nanostructures such as quantum dots, nanotubes, nanowires, and nanopillars has progressed rapidly over the past 10 years. However, both bottom-up and top-down methods to integrate the nanostructures are met with several challenges. For practical applications with the high level of the integration, an approach that can fabricate the required structures locally is desirable. In addition, the electrical signal to construct and control the nanostructures can provide significant advantages toward the stability and ordering. Through experiments on the negative resistance switching phenomenon in Pt-NiO-Pt structures, we have fabricated nanofilament channels that can be electrically connected or disconnected. Various analyses indicate that the nanofilaments are made of nickel and are formed at the grain boundaries. The scaling behaviors of the nickel nanofilaments were closely examined, with respect to the switching time, power, and resistance. In particular, the 100 nm x 100 nm cell was switchable on the nanosecond scale, making them ideal for the basis for high-speed, high-density, nonvolatile memory applications.

High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability

For the first time, we have successfully fabricated gate-all-around twin silicon nanowire transistor (TSNWFET) on bulk Si wafer using self-aligned damascene-gate process. With 10nm diameter nanowire, saturation currents through twin nanowires of 2.64 mA/mum, 1.11 mA/mum for n-channel TSNWFET and p-channel TSNWFET are obtained, respectively. No roll-off of threshold voltages, ~70 mV/dec. of substhreshold swing (SS), and ~20 mV/V of drain induced barrier lowering(DIBL) down to 30 nm gate length are observed for both n-ch and p-ch TSNWFETs

2-stack 1D-1R Cross-point Structure with Oxide Diodes as Switch Elements for High Density Resistance RAM Applications

We have successfully integrated a 2-stack 8times8 array 1D- lR (one diode-one resistor) structure with 0.5 mumtimes0.5 mum cells in order to demonstrate the feasibility of high density stacked RRAM. p-CuOx/n-InZnOx heterojunction thin film was used for the first time as a oxide diode which shows increased current density of two orders over our previous p-NiOx/n-TiOx oxide diode. And Ti-doped NiO was used for the storage node. No limitation to the number of stacks has been observed from our results. Cell and device properties of our cross-point structure 8times8 array are reported. In addition, all fabrication processes were done at room temperature without other dedicated facilities or processes allowing for compatibility with current CMOS technology. Bi-stable switching for 1D-1R memory was demonstrated for our 2-stack cross-point structures showing excellent behavior for both diode and storage nodes. The forward current density for p-CuOx/n-IZOx diodes was over 104A/cm2, and the operation voltage for the storage node with diode attached was around 3 V.

Fully Rollable Transparent Nanogenerators Based on Graphene Electrodes

[*] Prof. S.-W. Kim, H.-K. Park, J.-S. Seo School of Advanced Materials Science and Engineering SKKU Advanced Institute of Nanotechnology (SAINT) Center for Human Interface Nanotechnology (HINT) Sungkyunkwan University Suwon, 440-746 (Republic of Korea) E-mail: kimsw1@skku.edu Dr. J.-Y. Choi, Dr. D. Choi, Dr. W. M. Choi, H.-J. Shin, Dr. J. Park, S.-M. Yoon, Dr. S. Y. Lee, Dr. J. M. Kim Samsung Advanced Institute of Technology Yongin, Gyeonggi, 446-712 (Republic of Korea) E-mail: jaeyoung88.choi@samsung.com M.-Y. Choi School of Advanced Materials and System Engineering Kumoh National Institute of Technology Gumi, Gyeongbuk, 730-701 (Republic of Korea)

Phase-Change Behavior of Stoichiometric Ge2Sb2Te5 in Phase-Change Random Access Memory

We observed the atomic structures for each reset and set state in a phase-change random access memory fabricated using stoichiometric crystalline Ge 2 Sb 2 Te 5 . The reset state clearly showed a mixture of dome-shaped amorphous and crystal structure surrounding amorphous, but the set state showed abnormally grown large grains due to recrystallization of the amorphous structure. The crystal structure of the recrystallized grain was face-centered cubic. The element analysis indicated that the atomic composition changes to nonstoichiometric phase in the active regions of the reset and the set state, which is Sb-rich and Te-deficient compared to the pristine stoichiometric composition. Analysis showed that thermal interdiffusion of Sb and Te caused nonstoichiometric nature of the material to reach the energetically stable state in the active region.

p-GaN Gate HEMTs With Tungsten Gate Metal for High Threshold Voltage and Low Gate Current

The impact of gate metals on the threshold voltage (VTH) and the gate current of p-GaN gate high-electron-mobility transistors (HEMTs) is investigated by fabricating p-GaN gate HEMTs with different work function gate metals-Ni and W. p-GaN gate HEMTs incorporate a p-GaN layer under the gate electrode as the gate stack on top of the AlGaN/GaN layer. In comparison to the Ni-gate p-GaN HEMTs, the W-gate p-GaN HEMTs showed a higher VTH of 3.0 V and a lower gate current of 0.02 mA/mm at a gate bias of 10 V. Based on TCAD device simulations, we revealed that these high VTH and low gate current are attributed to the low gate metal work function and the high Schottky barrier between the p-GaN and the W gate metal.

Pd-nanocrystal-based nonvolatile memory structures with asymmetric SiO2∕HfO2 tunnel barrier

Pd nanocrystals (NCs) on asymmetric tunnel barrier (ATB) composed of stacked SiO2 and HfO2 layers have been employed for nonvolatile memory devices. The Pd-NC layers are formed by electrostatic self-assembly of negatively charged colloidal Pd NCs. The presence of isolated Pd NCs of ∼5nm embedded in HfO2 is confirmed by scanning and transmission electron microscopy images. Outstanding program∕erase (P∕E) properties from C‐V curves are observed with a memory window of 6V under ±17V. Extrapolation of the data up to ten years shows that the flatband voltage drops at the P∕E levels are maintained within only 1.0∕0.5V, respectively, resulting from the efficient data retention based on the ATB. These results are promising enough for the memory structure to be utilized for the multilevel charge storage.

CHARACTERIZATION OF FE-CATALYZED CARBON NANOTUBES GROWN BY THERMAL CHEMICAL VAPOR DEPOSITION

The growth of carbon nanotubes (CNTs) on Fe catalytic films by thermal chemical vapor deposition has been investigated. Fe thin films deposited on Si substrates agglomerate to nanoparticles after heat treatment. The Fe nanoparticles are easily oxidized to Fe2O3 after the synthesis, but the nanoparticles during the CNT synthesis are shown to be in the liquid iron phase due to the reducing force of NH3. This is revealed by cross-sectional transmission electron microscopy examinations of the nanoballs and the Fe inclusions along with relevant chemical analyses. The CNT growth mode and mechanism with a Fe catalyst was very similar to that with a Ni catalyst in thermal chemical vapor deposition method.

High‐Performance Nanowire Oxide Photo‐Thin Film Transistor

A gate-modulated nanowire oxide photosensor is fabricated by electron-beam lithography and conventional dry etch processing.. The device characteristics are good, including endurance of up to 10(6) test cycles, and gate-pulse excitation is used to remove persistent photoconductivity. The viability of nanowire oxide phototransistors for high speed and high resolution applications is demonstrated, thus potentially expanding the scope of exploitation of touch-free interactive displays.

Carrier lifetimes in type-II InAs quantum dots capped with a GaAsSb strain reducing layer

Carrier lifetimes have been measured for long-wavelength emitting InAs quantum dots (QDs) capped with a thin GaAsSb layer. Above a critical Sb composition, a type-II system is formed, resulting in an increase in the carrier lifetime. The carrier lifetime in a strongly type-II structure is increased by a factor ∼54 in comparison to the lifetime in a type-I structure. In addition, the type-II carrier lifetime varies across the inhomogeneously broadened ground-state emission, while the type-I QD lifetime is invariant.