Reinaldo A. Bergamaschi

Designing systerns-on--chip using cores

Leading-edge systems-on-chip (SoC) being designed today could reach 20 Million gates and 0.5 to 1 GHz operating frequency. In order to implement such systems, designers are increasingly relying on reuse of Intellectual property (IP) blocks. Since IP blocks are pre-designed and pre-verified, the designer can concentrate on the complete system without having to worry about the correctness or performance of the individual components. That is the goal, in theory. In practice, assembling on SoC using IP blocks is still an error-prone, labor-intensive and time-consuming process. This paper discusses the main challenges in SoC designs using IP blocks and elaborates on the methodology and tools being put in place at IBM for addressing the problem. It explains IBMs SoC architecture and gives algorithmic details on the high-level tools being developed for SoC design.

Control-flow versus data-flow-based scheduling: combining both approaches in an adaptive scheduling system

As high-level synthesis techniques gain acceptance among designers, it is important to be able to provide a robust system which can handle large designs in short execution times, producing high-quality results. Scheduling is one of the most complex tasks in high-level synthesis, and although many algorithms exist for solving the scheduling problem, it remains a main source of inefficiency by either not producing high-quality results, not taking into account realistic design requirements, or requiring unacceptable execution times. One of the main problems in scheduling is the dichotomy between control and data. Many algorithms to date have been able to provide scheduling solutions by looking only at either the data part or the control part of the design. This has been done in order to simplify the problem; however, it has resulted in many algorithms unable to handle efficiently large designs with complex control and data functionality. This paper presents algorithms for combining dataflow and control-flow techniques into a robust scheduling system. The main characteristics of this system are as follows: 1) it uses path-based techniques for efficient handling of control and mutual exclusiveness (for resource sharing), 2) it allows operation reordering and parallelism extraction within the context of path-based scheduling, 3) it contains a control partitioning algorithm for design space exploration as well as for reducing the number of control paths, and 4) it combines the above algorithms into an adaptive scheduling system which is capable of trading optimality for execution time on-the-fly. Results involving billions of paths are presented and analyzed.

Synthesis using path-based scheduling: algorithms and exercises

Path-based scheduling algorithms consider all possible sequences of operations (called paths) in a control-flow graph. Unlike most scheduling techniques used in high-level synthesis, they stress optimization across conditional branches. This paper presents several path-based algorithms. An exact algorithm finds the minimum number of control steps required for each possible path being executed. Heuristic solutions were also implemented. Extensive application of these algorithms to the benchmarks of the High-Level Synthesis Workshop showed the practical feasibility of such methods.

Timing analysis in high-level synthesis

A comprehensive timing model for behavioral-level specifications and algorithms for timing analysis in high-level synthesis is described. It is based on a timing network which models the data flow as well as the control flow in the behavioral input specification. The delay values for the network modules are created by invoking the same logic synthesis procedure applied after behavioral synthesis. The timing network is built only once for a given behavioral description. Several parameters are used to explore different scheduling possibilities as well as different optimization modes (area, delay), without changing the network. The use of the timing model in conjunction with a path-based scheduling algorithm is presented. Results for several benchmarks attested to the accuracy of this approach.<<ETX>>

Generalized resource sharing

Resource sharing is one of the main tasks in high-level synthesis, and although many algorithms have addressed the problem there are still several limitations which restrict the generality and applicability of current algorithms. Most clique-partitioning-based algorithms use local and inaccurate cost-functions which result in inefficient results. This paper presents algorithms for the resource sharing problem on registers and functional units, and shows how they overcome the limitations of existing algorithms. The main characteristics of this work are: interleaved register and functional unit merging in a global clique partitioning based framework, accurate merging cost estimation, accurate interconnect cost estimation, relative control cost taken into account and efficient false loop elimination. The results obtained show significant improvements in the delay of designs, while also minimizing area, specially for large designs with many sharing possibilities.

The effects of false paths in high-level synthesis

The author discusses the effects of false paths and their consequences in scheduling and allocation during high-level synthesis. False paths through the control-flow graph may occur due to sequences of conditional operations. The detection of false paths during scheduling may result in a smaller number of states, improved operator sharing, and smaller control logic. A heuristic algorithm is presented for the detection and elimination of false paths during path-based scheduling. Results for benchmark examples are presented. For the designs which contained false paths, the percentage of false paths varied from 5% to 83%. A reduction of 15% in the final cell count for one benchmark was obtained by eliminating false paths. Even though the proposed algorithm is heuristic and cannot guarantee the detection of all false paths, it did find all false paths in the small to medium size examples tried. In most cases the condition trees are small, with few data dependencies, which increases the probability of a false path being found by the algorithm.<<ETX>>

Exploring power management in multi-core systems

Power dissipation has become a critical design metric in microprocessor-based system design. In a multi-core system, running multiple applications, power and performance can be dynamically traded off using an integrated power management (PM) unit. This PM unit monitors the performance and power of each core and dynamically adjusts the individual voltages and frequencies in order to maximize system performance under a given power budget (usually set by the operating system). This paper presents a performance and power analysis methodology, featuring a simulation model for multi-core systems that can be easily reconfigured for different scenarios and a PM infrastructure for the exploration and analysis of PM algorithms. Two algorithms have been implemented: one for discrete and one for continuous power modes based on non-linear programming. Extensive experiments are reported, illustrating the effect of power management both at the core and the chip level.

The A to Z of SoCs

The exploding complexity of new chips and the ever decreasing time-to-market window are forcing fundamental changes in the way systems are designed. The advent of Systems-on-Chip (SoC) based on pre-designed intellectual-property (IP) cores has become an absolute necessity for embedded systems companies to remain competitive. Designing an SoC, however, is extremely complex, as it encompasses a range of difficult problems in hardware and software design. This paper explains a wide range of SoC issues including market drivers and trends, technology and integration aspects, early architecture definition, methodology, hardware and software design and verification techniques.

State-based power analysis for systems-on-chip

Early power analysis for systems-on-chip (SoC) is crucial for determining the appropriate packaging and cost. This early analysis commonly relies on evaluating power formulas for all cores for multiple configurations of voltage, frequency, technology and application parameters, which is a tedious and error-prone process. This work presents a methodology and algorithms for automating the power analysis of SoCs. Given the power state machines for individual cores, this work defines the product power state machine for the whole SoC and uses formal symbolic simulation algorithms for traversing and computing the minimum and maximum power dissipated by sets of power states in the SoC.

The IBM High-Level Synthesis System

The High-level IBM Synthesis system HIS is the result of ongoing efforts at the T.J. Watson Research Center, the Advanced Business Systems Division and IBM’s Electronic Design Systems. The main goal is to explore design automation for synchronous digital systems at levels above the logic level in a practical environment.