Indranil Hatai

An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis

This paper proposes an efficient constant multiplier architecture based on vertical-horizontal binary common sub-expression elimination (VHBCSE) algorithm for designing a reconfigurable finite impulse response (FIR) filter whose coefficients can dynamically change in real time. To design an efficient reconfigurable FIR filter, according to the proposed VHBCSE algorithm, 2-bit binary common sub-expression elimination (BCSE) algorithm has been applied vertically across adjacent coefficients on the 2-D space of the coefficient matrix initially, followed by applying variable-bit BCSE algorithm horizontally within each coefficient. This technique is capable of reducing the average probability of use or the switching activity of the multiplier block adders by 6.2% and 19.6% as compared to that of two existing 2-bit and 3-bit BCSE algorithms respectively. ASIC implementation results of FIR filters using this multiplier show that the proposed VHBCSE algorithm is also successful in reducing the average power consumption by 32% and 52% along with an improvement in the area power product (APP) by 25% and 66% compared to those of the 2-bit and 3-bit BCSE algorithms respectively. As regards the implementation of FIR filter, improvements of 13% and 28% in area delay product (ADP) and 76.1% and 77.8% in power delay product (PDP) for the proposed VHBCSE algorithm have been achieved over those of the earlier multiple constant multiplication (MCM) algorithms, viz. faithfully rounded truncated multiple constant multiplication/accumulation (MCMAT) and multi-root binary partition graph (MBPG) respectively. Efficiency shown by the results of comparing the FPGA and ASIC implementations of the reconfigurable FIR filter designed using VHBCSE algorithm based constant multiplier establishes the suitability of the proposed algorithm for efficient fixed point reconfigurable FIR filter synthesis.

A new high-performance digital FM modulator and demodulator for software-defined radio and its FPGA implementation

This paper deals with an FPGA implementation of a high performance FM modulator and demodulator for software defined radio (SDR) system. The individual component of proposed FM modulator and demodulator has been optimized in such a way that the overall design consists of a high-speed, area optimized and low-power features. The modulator and demodulator contain an optimized direct digital frequency synthesizer (DDFS) based on quarter-wave symmetry technique for generating the carrier frequency with spurious free dynamic range (SFDR) of more than 64 dB. The FM modulator uses pipelined version of the DDFS to support the up conversion in the digital domain. The proposed FM modulator and demodulator has been implemented and tested using XC2VP30-7ff896 FPGA as a target device and can operate at a maximum frequency of 334.5 MHz and 131 MHz involving around 1.93 K and 6.4 K equivalent gates for FM modulator and FM demodulator respectively. After applying a 10 KHz triangular wave input and by setting the system clock frequency to 100 MHz using Xpower the power has been calculated. The FM modulator consumes 107.67 mW power while FM demodulator consumes 108.67 mW power for the same input running at same data rate.

Reconfigurable Architecture of a RRC Fir Interpolator for Multi-standard Digital Up Converter

This paper proposes a low-power, high-speed architecture of a reconfigurable root-raised cosine (RRC) filter which serves as a major component of a digital up converter (DUC). The proposed RRC filter can be reconfigured at any time to suit one of three different interpolation factors and one of two different roll-off factors pertaining to various modern wireless communication standards. The fact that the design is multiplexer-based has ensured reduction in power consumption. In addition, transposed direct form II realization of the RRC filter has enabled maximum operating frequency by placing a set of registers at proper locations of the data path. Power consumption of an FPGA implementation of the proposed filter has been found to be about 234 mW at 50 MHz clock frequency. However, the designed filter is capable of operating at a maximum clock frequency of 229 MHz on XC2VP30 FPGA devices while requiring only 7K gates. Significant reduction in area and power of the proposed RRC filter makes it very suitable for an area critical power efficient reconfigurable multi-standard DUC.

A high-speed, ROM-less DDFS for software defined radio system

A recent trend in the research of ROM-less DDFS architecture, which is endowed with high speed, low power and high SFDR features and will generate the sine or cosine waveforms within a broad frequency range. In this work one high-speed, low-power, and low-latency pipelined ROM-less DDFS has been proposed and implemented in Xilinx Virtex-II Pro FPGA. The proposed ROM-less DDFS design has 32 bit phase input and 16 bit amplitude resolution with maximum amplitude error of 1.5×10−4. The FPGA implementation of the proposed design has an SFDR of −94.3 dBc and maximum operation frequency of 276 MHz by consuming only 22 K gate and 1.05 mW/MHz power. The high speed of operation and low power makes the propose design suitable for the use in communication transceiver for the up and down conversion.

FPGA Implementation of a Digital FM Modem

In this paper an FPGA implementation of a high performance programmable digital FM modem has been done for targeting towards the Software Defined Radio (SDR) application. The proposed design consists of the reprogrammable, area optimized and low-power features. The modulator and demodulator contain a compressed direct digital synthesizer (DDS) for generating the carrier frequency with spurious free dynamic range of more than 70 dB. The demodulator has been implemented based on the digital phase locked loop (DPLL) technique. The same DDS has been used for demodulating the modulated signal. The proposed FM modem has been implemented and tested using Virtex2Pro University board as a target device. Implementation of the FM modem can run maximum 103 MHz, by taking less than 8k gate equivalent in the XC2VP-30 FPGA device.

An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation

This brief proposes a two-step optimization technique for designing a reconfigurable VLSI architecture of an interpolation filter for multistandard digital up converter (DUC) to reduce the power and area consumption. The proposed technique initially reduces the number of multiplications per input sample and additions per input sample by 83% in comparison with individual implementation of each standards filter while designing a root-raised-cosine finite-impulse response filter for multistandard DUC for three different standards. In the next step, a 2-bit binary common subexpression (BCS)-based BCS elimination algorithm has been proposed to design an efficient constant multiplier, which is the basic element of any filter. This technique has succeeded in reducing the area and power usage by 41% and 38%, respectively, along with 36% improvement in operating frequency over a 3-bit BCS-based technique reported earlier, and can be considered more appropriate for designing the multistandard DUC.

ASIC implementation of a 512-point FFT/IFFT processor for 2D CT image reconstruction algorithm

The CT scan medical imaging requires huge amount of computations for reconstructing the images. Modified Fast Radon Transform (MFRT) uses FFT based parallel algorithm for reconstruction of 2D/3D CT images from its sonogram data using convolution operation by concurrent 1D FFT/IFFT and matrix multiplications. To achieve optimum hardware utilization with low power consumption an FFT module, based on iterative radix-2 decimation in frequency (DIF) algorithm, has been designed and implemented. The module has been designed in such way so that it can also be used for IFFT computation only by changing a single parameter. To compute the FFT, the twiddle factor has been calculated using Coordinate Rotation Digital Computer (CORDIC), by steering the data properly in the butterfly structure. The synthesized frequency of FFT/IFFT module is 220 MHz and gate count is 1,040,136 using 130 nm faraday digital libraries. The power has been analyzed using prime power and the value of the power consumption is 15mW. The designed FFT/IFFT ASIC chip is very much suitable for low-area and low power biomedical applications like CT image reconstruction, Doppler wave spectrogram etc.

A novel low-latency, high-speed DDFS architecture

A recent trend in the research of ROM-less DDFS architecture, which is endowed with high speed, low power and high SFDR features and will generate the sine or cosine waveforms within a broad frequency range. In this work one high-speed, low-power, and low-latency (requires 11 clock cycles) pipelined ROM-less DDFS has been proposed and implemented in Xilinx Virtex-II Pro FPGA. The proposed ROM-less DDFS design has 32 bit phase input and 16 bit amplitude resolution with maximum amplitude error of 1.5×10−4. The FPGA implementation of the proposed design has an SFDR of −94.3 dBc and maximum operation frequency of 276 MHz by consuming only 22 K gate and 1.05 mW/MHz power. The high speed of operation and low power makes the propose design suitable for the use in communication transceiver for the up and down conversion.

FPGA implementation of a fetal heart rate measuring system

Labor during pregnancy is an inherently dangerous life event for a live fetus and its mother. Non-invasive method of Fetal Heart Rate (FHR) measuring system helps to reduce Infant Mortality Rate (IMR) by continuous monitoring of the fetus heart rate. In this paper real-time implementation of a FHR measuring system has been developed using Xilinx Spartan-6 FPGA device, which can calculate the fetus heart rate and display ECG signal through HDMI port. In FHR extraction of the cleaned fetal ECG signal from the maternal ECG is the main challenge. In our proposed work Least Mean Square (LMS) adaptive filter has been used as the adaptive noise canceller along with dynamic thresholding technique for de-noising the fetus ECG signal and helps to achieve 88% accuracy in the proposed FHR system. FPGA implementation of the FHR system consumes 7.8K slices and can achieve sampling frequency of 80 MHz while implemented on XC6SLX45-3CSG484 FPGA device. The comparison results show that our proposed design is more efficient than the literature reported earlier.

A High-Speed Low-Power Low-Latency Pipelined ROM-Less DDFS

The present-day research on direct digital frequency synthesizer (DDFS) lays emphasis on ROM-less architecture, which is endowed with high speed, low power and high spurious free dynamic range (SFDR) features. The DDFS has a wide application in signal processing and telecommunication area, which generates the sine or cosine waveforms within a broad frequency range. In this paper, one high-speed, low-power, and low-latency pipelined ROM-less DDFS architecture has been proposed, implemented and tested using Xilinx Virtex-II Pro University FPGA board. The proposed ROM-less DDFS design has 32 bit phase input and 16 bit amplitude resolution with a maximum amplitude error of 1.5 ×10− 4. FPGA implementation of the proposed design has exhibited an SFDR of -94.3 dBc and a maximum operating frequency of 276 MHz while consuming only 22 K gates and 1.05 mW/MHz power. The high speed of operation and the low power make the proposed design suitable for use in communication transceiver for up and down conversion.