Kaushik Bhattacharyya

A Low Voltage, Low Ripple, on Chip, Dual Switch-Capacitor Based Hybrid DC-DC Converter

Here we propose a low voltage low ripple dual switch- capacitor based hybrid DC-DC converter which is suitable for high dropout embedded regulation. In the proposed topology, along with a linear regulator two switching capacitors are used to store and recycle the charge for better power efficiency. The linear regulator is used to reduce the amount of output voltage ripple that comes from the switching capacitors. The output ripple noise is further reduced by introducing a synthesized counter ripple through the linear regulator. With this noise reduction technique, for an acceptable output ripple noise, the switching capacitors are reduced to a value which can be implemented on chip. The proposed converter circuit is designed in 0.18 mu process for 3.3 V to 1.25 V conversion. With two switching capacitors of 150 pF each, for 10 mA load current and 50 pF load capacitor, peak-peak output voltage ripple is only 45 mV and the achieved power efficiency is 64%.

Architectural design and FPGA implementation of radix-4 CORDIC processor

A new scaled radix-4 CORDIC architecture that incorporates pipelining and parallelism is presented. The latency of the architecture is n/2 clock cycles and throughput rate is one valid result per n/2 clocks for n bit precision. A 16 bit radix-4 CORDIC architecture is implemented on the available FPGA platform. The corresponding latency of the architecture is eight clock cycles and throughput rate is one valid result per eight clock cycles. The entire scaled architecture operates at 56.96MHz of clock rate with a power consumption of 380mW. The speed can be enhanced with the upgraded version of FPGA device. A speed-area optimized processor is obtained through this architecture and is suitable for real time applications.

Improvement of power efficiency in switched capacitor DC-DC converter by shoot-through current elimination

This paper presents a non overlapped rotational time interleaving scheme to eliminate shoot-through current in switched capacitor dc-dc converters. In addition to the improvement of power efficiency this scheme also reduces the output voltage ripple. In the integrated converter, current regulation control is incorporated with the basic switched capacitor converter to get the output voltage at a pre-specified level. The proposed converter has been designed in 0.18μm CMOS process with a total flying capacitance of 330pF and load capacitance of 50pF. The capacitors are chosen such that on-chip implementation is possible. The basic switched capacitor converter provides 3.3V to 1.45V conversion and achieves power efficiency of 80.7% and output voltage ripple of 5.7mV at 10mA output current. For the same output current the integrated converter achieves a power power efficiency of 73.5% and output voltage ripple of 5mV for 1.35V output voltage.

Technique for the reduction of output voltage ripple of switched capacitor-based DC-DC converters

Switch capacitor DC-DC converter is an emerging concept for high dropout application. This paper discusses techniques for output voltage ripple reduction of an embedded dual-switch capacitor - linear regulator-based hybrid DC-DC converter. In spite of deploying the advantage of PSRR property of the linear regulator, the ripple at the output of the convertor is still high. To alleviate this, a new technique of further reduction of the output ripple by introducing synthesised counter ripples through the linear regulator is presented. The conventional and new technique of ripple reduction has been analysed with the help of small signal equivalent circuits. These techniques have been implemented with a hybrid converter for 3.3-V-to-1.35-V conversions. A test chip is fabricated in a 0.18--m standard digital CMOS process to demonstrate the efficacy of the proposed technique. It is found that the trend of ripple reduction by ripple synthesiser in measured results is consistent with the simulation results and also observed in the measured results that the ripple synthesiser reduces the output ripple of a hybrid converter by the factor of 0.52 and 0.45 for the load current of 2.2-mA and 7.3-mA, respectively.

Embedded hybrid DC-DC converter with improved power efficiency

This paper deals with the efficiency improvement of an embedded hybrid DC-DC converter which is suitable for high dropout embedded regulation. In the proposed topology, power efficiency is improved by eliminating shoot-through current of switched-Capacitor module using Non-overlapped Rotational Time Interleaving (NRTI) switching scheme. In addition to the improvement in power efficiency, this scheme also reduces output voltage ripple. As the output of the switched capacitor network is a function of load current and switching frequency, the switched capacitor network is cascaded with a linear regulator to get line and load regulation. The proposed hybrid converter circuit is designed in 0.18µ process for 3.3V to 1.25V conversion. With total flying capacitance of 330pF, for 15.5 mA of load current and 50pF load capacitor, peak-peak output voltage ripple is only 6 mV and the achieved power efficiency is 70%

A Low Voltage, Low Ripple on Chip Hybrid DC-DC Converter

Here we propose a low voltage low ripple hybrid dc-dc converter. In the proposed topology, along with a linear regulator a switching capacitor is used to store and recycle the charge for better power efficiency. Linear regulator is used to reduce the amount of output voltage ripple that comes from the switching capacitor. The output noise is further reduced by introducing a synthesized counter noise through the linear regulator. With this noise reduction technique, for an acceptable output ripple noise, the switching capacitor is reduced to a value which can be implemented on chip. The proposed converter circuit is designed in 0.18 mu process for 3.3 V to 1.25 V conversion. With 950 pF switching capacitor, for 9.5 mA load current and 100 pF load capacitor, peak-peak output voltage ripple is 75 mV and the power efficiency is 77%.

IMPROVEMENT OF POWER EFFICIENCY AND OUTPUT VOLTAGE RIPPLE OF EMBEDDED DC–DC CONVERTERS WITH THREE STEP DOWN RATIOS

In this paper three embedded switched capacitor based DC–DC converters targeting Vdd/2, 2Vdd/3, and Vdd/3 output voltages have been designed with improved power efficiency and output voltage ripple. The performance of each of the converter is improved by nonoverlapped rotational time interleaving (NRTI) switching scheme. Current regulation scheme is included with each of the above NRTI switched capacitor converter to achieve better load and line regulation. The proposed converters are designed and simulated in a 0.18 μm n-well CMOS process with the total flying capacitance of 330 pF and load capacitor of 50 pF. The capacitance values are kept within on-chip implementable range. The maximum power efficiency and the output voltage ripple of the integrated NRTI DC–DC converters targeted for Vdd/2, 2Vdd/3 and Vdd/3 output generation are 71.5% and 5 mV, 69.23% and 13.27 mV and 58.09% and 10.5 mV, respectively.

Design and implementation of a switched capacitor-based embedded hybrid DC–DC converter

Here, we propose an integrated hybrid DC–DC converter suitable for high drop-out energy conscious applications. In the hybrid converter topology, along with a linear regulator two switched capacitors are used to store and recycle charge for better power efficiency. Without significant power loss the switched capacitors step down the supply voltage for the linear regulator working in low drop-out mode. The linear regulator, on the other hand, attenuates the voltage ripple that originates from the switched capacitors converter on its power supply rejection ratio. It also helps for line and load regulation. Additionally, a synthesised counter ripple is injected through the linear regulator to further reduce the output ripple. With these two techniques, for a moderate load current and an acceptable output ripple, the switching and load capacitors are reduced to a value which can be implemented within the chip. The proposed integrated converter circuit has been designed, implemented and tested in a 0.18 mm CMOS process for 3.3–1.3V conversion. With two switching capacitors of 210 pF each and 100 pF load capacitor, more than 13 mA of load current, measured peak-to-peak output voltage ripple is 146 mV. The achieved measured power efficiency is 64.97%. Exhaustive silicon characterisation of the converter is done to observe the power efficiency and ripple variation at different frequency of operations.

A dynamically reconfigurable NRTI switched-capacitor-based hybrid DC-DC converter suitable for embedded applications

In this paper, a dynamically reconfigurable, Non-overlap Rotational Time Interleaved (NRTI) switched capacitor (S-C) DC-DC converter is presented. Its S-C module is reconfigurable to generate three different fractions (viz., 1/3, 1/2 and 2/3) of its input supply (Vdd). This maintains good power efficiency while its output voltage gets adjusted over a large range. In addition, a load-current-sensing circuit is integrated within it to dynamically reconfigure the S-C module based on the required driving capability. This feature enables to extend load current range to higher limit and at the same time improves the power efficiency in low load current regime. The S-C module is integrated with a current control loop for load and line regulation.The proposed architecture is simulated in a 0.18µm CMOS process using dual oxide transistors to demonstrate the efficacy of the proposed topology. The input supply voltage is 3.3V and the regulated output range is 0.8-1.6V. Total flying capacitance is 330pF and the load capacitor value is 50pF. For an output of 1.35V, its power efficiency is maintained above 50% over a load current range of 4-17.6mA with a peak of 66% at 9mA. Throughout this current range the output voltage ripple remains within 12mV.

An approach to design and implementation of on-chip clock generator for the switched capacitor based embedded DC-DC converter

Here, the design and implementation of an on-chip clock generator which is needed for a switched capacitor based embedded DC-DC converter is described. The strategies that should be taken during making the design by predicting the occurrence of the parasitic issues at the time of implementation to keep the performance of the clock generator at per in silicon are also elaborated. The reported measurement results closely match with the simulation results in clock generation. It can be a helpful tutorial paper to design and implement an on-chip clock generator suitable for mid-frequency, real time applications.