Indrajit Chakrabarti

An improved low-power high-throughput log-MAP turbo decoder

This paper presents an efficient implementation of a high-throughput low-power turbo decoder. The design of the component decoder has been optimized so as to achieve low power implementation of the turbo decoder. A collision-free interleaver has been designed for appropriate parallel decoding operations. Performance enhancing techniques such as parallel processing and pipelining have been applied to realize the highly recursive and complex maximum a posteriori probability (MAP) decoder. Area, power and throughput of the proposed decoder architecture compare favorably with those of an architecture which has been recently reported in literature. The designed decoder, which achieves a throughput of 930 Mbps while consuming 265 mW of power, can be considered to be suitable for a number of real time applications.

An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis

This paper proposes an efficient constant multiplier architecture based on vertical-horizontal binary common sub-expression elimination (VHBCSE) algorithm for designing a reconfigurable finite impulse response (FIR) filter whose coefficients can dynamically change in real time. To design an efficient reconfigurable FIR filter, according to the proposed VHBCSE algorithm, 2-bit binary common sub-expression elimination (BCSE) algorithm has been applied vertically across adjacent coefficients on the 2-D space of the coefficient matrix initially, followed by applying variable-bit BCSE algorithm horizontally within each coefficient. This technique is capable of reducing the average probability of use or the switching activity of the multiplier block adders by 6.2% and 19.6% as compared to that of two existing 2-bit and 3-bit BCSE algorithms respectively. ASIC implementation results of FIR filters using this multiplier show that the proposed VHBCSE algorithm is also successful in reducing the average power consumption by 32% and 52% along with an improvement in the area power product (APP) by 25% and 66% compared to those of the 2-bit and 3-bit BCSE algorithms respectively. As regards the implementation of FIR filter, improvements of 13% and 28% in area delay product (ADP) and 76.1% and 77.8% in power delay product (PDP) for the proposed VHBCSE algorithm have been achieved over those of the earlier multiple constant multiplication (MCM) algorithms, viz. faithfully rounded truncated multiple constant multiplication/accumulation (MCMAT) and multi-root binary partition graph (MBPG) respectively. Efficiency shown by the results of comparing the FPGA and ASIC implementations of the reconfigurable FIR filter designed using VHBCSE algorithm based constant multiplier establishes the suitability of the proposed algorithm for efficient fixed point reconfigurable FIR filter synthesis.

Reconfigurable Architecture of a RRC Fir Interpolator for Multi-standard Digital Up Converter

This paper proposes a low-power, high-speed architecture of a reconfigurable root-raised cosine (RRC) filter which serves as a major component of a digital up converter (DUC). The proposed RRC filter can be reconfigured at any time to suit one of three different interpolation factors and one of two different roll-off factors pertaining to various modern wireless communication standards. The fact that the design is multiplexer-based has ensured reduction in power consumption. In addition, transposed direct form II realization of the RRC filter has enabled maximum operating frequency by placing a set of registers at proper locations of the data path. Power consumption of an FPGA implementation of the proposed filter has been found to be about 234 mW at 50 MHz clock frequency. However, the designed filter is capable of operating at a maximum clock frequency of 229 MHz on XC2VP30 FPGA devices while requiring only 7K gates. Significant reduction in area and power of the proposed RRC filter makes it very suitable for an area critical power efficient reconfigurable multi-standard DUC.

A normal factor graph approach for co-operative spectrum sensing in cognitive radio

In this paper, normal factor graph (NFG) based probabilistic inference approach for the cooperative spectrum sensing in cognitive radio (CR) is presented. Spectrum sensing problem is modeled as binary hypothesis testing problem. We have formulated the joint probability function with all latent and manifest variables which describe the system. Then decompose the joint distribution function into simpler conditional probability functions and represent them through normal factor graph. The exact marginalization is computed by passing the messages (probability values) among the nodes and edges using Sum-product-algorithm (SPA) / Belief-propagation (BP) algorithm. We compute messages for null and alternate hypothesis and apply Neyman-Pearson (NP) theorem based Likelihood ratio test (LRT) for optimal decision at fusion center. We consider non-central chi-square distribution for alternate hypothesis (H1). It is assumed that secondary users (SUs) are independently sensing the primary user (PU), therefore the graph has no cycle. It is employing energy detector based local sensing with hard decision. We consider non-ideal channel conditions for both PU-SU and SU-FC channels. Initially flat-fading, time-invariant channels with AWGN between PU-SUs and binary symmetric channels (BSC) and AWGN channels between SUs and fusion center (FC) are considered. Simulation results show that proposed methods improves the performance of the cooperative spectrum sensing.

Motion Estimation for Video Coding

Video data consist of a time sequence of image frames, and there exists a significant redundancy in temporal domain. One of the important aims of video compression is removal of the temporal redundancy in an efficient way. Motion Estimation (ME), which tries to remove the temporal redundancy by finding the best matching block in a reference frame for each block in the present frame, is the principal component of a video encoding system. Of all the components of a video encoder, the ME module consumes the lion’s share of overall power. A very simple arithmetic computation is required for ME. However, frequent memory access associated with ME affects the overall speed of operation and the power consumption. The present work has therefore focused on design and development of several fast ME architectures characterized by high processing speed, low power, and low area making them suitable for portable video application devices that are typically operated by battery power and involve real time operation. VLSI architecture has been developed for Fast Three Step Search (FTSS) algorithm that is used in video conferencing applications. An intelligent data arrangement has been used in this design to reduce the power consumption and to achieve a high speed of operation. Parallel VLSI architectures for Successive Elimination algorithm (SEA) have also been developed. The architecture proposed for SEA requires nearly 60 % less time with same power requirement and accuracy, but somewhat more area while being compared to an architecture meant for realizing full search algorithm. Moreover, the present work has conceived fast ME by combining One Bit Transformation (1BT) for fixed block size and single reference frame. Fast 1BT based ME architectures for variable block size and single reference frame and multiple reference frames have also been developed. The scope of the present work also includes fast ME algorithms based on the pixel truncation. An appropriate architecture has also been developed for implementing the proposed ME algorithm. In the present work, all the proposed architectures have been synthesized and analyzed for power and maximum operating frequencies in FPGA as well as ASIC platforms. Nowadays, the consumer looks out for the best possible video quality regardless of his/her location and degree of network support. To realize this however, the

An Improved Double Byte Error Correcting Code Using Cellular Automata

Cellular Automata(CA) based VLSI implementation of t-byte errors correcting code has been established by previous research to be superior to the other existing techniques employed for realizing Reed-Solomon(RS) code. However, the scheme suffers from the limitation that it can correct ti¾?byte errors (ti¾? 2) provided errors are confined either wholly to the information bytes or entirely to the check bytes. The work reported in the present paper overcomes this limitation and corrects the errors likely in both information and check bytes. Moreover one weakness found in an earlier similar work has been identified and rectified using a modified check symbol expressions.

Factor Graph Based Cooperative Spectrum Sensing in Cognitive Radio over Time-Varying Channels

A normal factor graph (NFG) based approach for cooperative spectrum sensing in cognitive radio over time varying and frequency non-selective fading channels is presented in this paper. An NFG based representation of a distributed cognitive radio system is first presented and then a Sum-Product- Algorithm (SPA) based analysis is developed for inference. The spectrum sensing problem is modelled as a distributed binary hypothesis testing problem. A Neyman-Pearson (NP) based likelihood ratio test statistic is derived for optimal sensing. As exact theoretical analysis of the system level probability of detection and probability of false alarm is very difficult, we provide an approximation which performs satisfactorily in the moderate to high signal-to-noise ratio (SNR) regime. The proposed NFG based spectrum sensing approach is computationally scalable to large networks and performs well under time varying channel conditions. Extensive simulation results are provided to validate our proposed approximation.

A high-speed, ROM-less DDFS for software defined radio system

A recent trend in the research of ROM-less DDFS architecture, which is endowed with high speed, low power and high SFDR features and will generate the sine or cosine waveforms within a broad frequency range. In this work one high-speed, low-power, and low-latency pipelined ROM-less DDFS has been proposed and implemented in Xilinx Virtex-II Pro FPGA. The proposed ROM-less DDFS design has 32 bit phase input and 16 bit amplitude resolution with maximum amplitude error of 1.5×10−4. The FPGA implementation of the proposed design has an SFDR of −94.3 dBc and maximum operation frequency of 276 MHz by consuming only 22 K gate and 1.05 mW/MHz power. The high speed of operation and low power makes the propose design suitable for the use in communication transceiver for the up and down conversion.

FPGA Implementation of a Digital FM Modem

In this paper an FPGA implementation of a high performance programmable digital FM modem has been done for targeting towards the Software Defined Radio (SDR) application. The proposed design consists of the reprogrammable, area optimized and low-power features. The modulator and demodulator contain a compressed direct digital synthesizer (DDS) for generating the carrier frequency with spurious free dynamic range of more than 70 dB. The demodulator has been implemented based on the digital phase locked loop (DPLL) technique. The same DDS has been used for demodulating the modulated signal. The proposed FM modem has been implemented and tested using Virtex2Pro University board as a target device. Implementation of the FM modem can run maximum 103 MHz, by taking less than 8k gate equivalent in the XC2VP-30 FPGA device.

VLSI design of fast fractal image encoder

A fast search based architecture for fractal image encoder, which efficiently exploits parallelism, is proposed. Speed up in encoding is achieved through parallel processing by finding data independency in different mathematical operations carried out in fractal encoding. This architecture requires 531 milli seconds to encode a 256×256 gray scale image at maximum clock frequency of 73.11 MHz. Thus, proposed architecture can be considered as a successful approach for real time application for image compression.