Indumini Ranmuthu

An analog front-end signal processor for a 64 Mb/s PRML hard-disk drive channel

Synchronous channel designs, such as partial response maximum likelihood (PRML), are viable for high areal density on a hard-disk drive (HDD). Previously-published PRML channels include a 56 Mb/s channel design but without an on-chip programmable filter, synthesizer or servo demodulator. This 5V BiCMOS integrated circuit contains all the analog front-end functions necessary for a 64Mb/s HDD channel using a rate-8/9 code.<<ETX>>

An analog front-end signal processor for a 64 Mbits/s PRML hard-disk drive channel

This BiCMOS IC contains all the analog front-end components necessary for the design of a 21-64 Mb/s HDD channel. Major functional blocks include an automatic gain control circuit having both analog and digital modes of operation, a programmable filter with 6-33 MHz bandwidth range, two phase-locked loops with 24-72 MHz center frequency ranges, a differential 6 bit flash A/D converter with 24-72 MHz sampling rates, and a write precompensator having 600 ps step size. >

A design for high noise rejection in a pseudodifferential preamplifier for hard disk drives

A study of supply and system noise rejection for a pseudodifferential amplifier is presented in this paper. This pseudodifferential amplifier is aimed at high data-rate disk drive signal sensing and preamplification applications. This high rejection was achieved by improving the rejection of the pseudodifferential amplifier and also by carefully designing the interconnect flex circuit where the preamplifier is mounted. The measured rejection to power supply, ground and system noise is above 50 dB over a 300 MHz bandwidth. This is significant for a pseudodifferential amplification system. The gain of the preamplifier is 47 dB and write mode to read mode switching time is 210 ns. This preamplifier currently supports disk drive data rates over 270 Mb/s.