Benjamin Sheahan

An analog front-end signal processor for a 64 Mb/s PRML hard-disk drive channel

Synchronous channel designs, such as partial response maximum likelihood (PRML), are viable for high areal density on a hard-disk drive (HDD). Previously-published PRML channels include a 56 Mb/s channel design but without an on-chip programmable filter, synthesizer or servo demodulator. This 5V BiCMOS integrated circuit contains all the analog front-end functions necessary for a 64Mb/s HDD channel using a rate-8/9 code.<<ETX>>

An analog front-end signal processor for a 64 Mbits/s PRML hard-disk drive channel

This BiCMOS IC contains all the analog front-end components necessary for the design of a 21-64 Mb/s HDD channel. Major functional blocks include an automatic gain control circuit having both analog and digital modes of operation, a programmable filter with 6-33 MHz bandwidth range, two phase-locked loops with 24-72 MHz center frequency ranges, a differential 6 bit flash A/D converter with 24-72 MHz sampling rates, and a write precompensator having 600 ps step size. >

A 3-V 4.25-Gb/s Laser Driver with 0.4-V Output Voltage Compliance

The design of a 155-Mb/s-4.25-Gb/s laser driver in SiGe BiCMOS is described. A large output voltage compliance range that allows DC coupling to the laser diode is achieved with a translinear pseudo-differential output driver. Active back-termination is provided at the modulation output pins. Careful design of the level shift stage affords low deterministic jitter over a very wide range of bit rates. The dynamic performance is preserved over a wide range of modulation current with a segmented driver slice scheme

A 3V, 4.25Gb/s laser driver with 0.4V output voltage compliance

The design of a 155Mb/s-4.25Gb/s laser driver in SiGe BiCMOS is described. A large output voltage compliance range that allows DC coupling to the laser diode is achieved with a translinear pseudodifferential output driver. Active back-termination is provided at the modulation output pins. Careful design of the level shift stage affords low deterministic jitter over a very wide range of bit rates. The dynamic performance is preserved over a wide range of modulation current with a segmented driver slice scheme.

4.25 Gb/s laser driver: design challenges and EDA tool limitations

This paper describes the design methodology, simulation, and tools used to design a 4.25 Gb/s high output swing laser driver (LD) and the electrical to optical interface from the LD to the laser diode. The quality of the optical output of a fiber optic communication channel is mainly determined by the LD and the electrical interface from the LD to the laser diode. Of particular importance in the interface is how well the LD overcomes the impact of the parasitic, resistive, capacitive, and inductive elements associated with the bondpad, bondwires, package, PCB transmission lines, passive components, and laser diode and its bondwires. The EDA tools used to model the electrical parasitics focus on RF and microwave applications and provide high frequency S-parameter models. This environment requires a stable time domain model of the electrical to optical interface. The presented LD integrated circuit operates from 155 Mb/s to 4.25 Gb/s with rise and fall times of 70 ps or less and a wide output voltage range, and a modulation current range of 5 mA to 85 mA