Ingmar Neumann

Cell replication and redundancy elimination during placement for cycle time optimization

Presents a new timing-driven approach for cell replication tailored to the practical needs of standard cell layout design. Cell replication methods have been studied extensively in the context of generic partitioning problems. However, until now, it has remained unclear what practical benefit can be obtained from this concept in a realistic environment for timing-driven layout synthesis. Therefore, this paper presents a timing-driven cell replication procedure, demonstrates its incorporation into a standard cell placement and routing tool, and examines its benefit on the final circuit performance in comparison with conventional gate or transistor sizing techniques. Furthermore, we demonstrate that cell replication can deteriorate the stuck-at fault testability of circuits and show that stuck-at redundancy elimination must be integrated into the placement procedure. Experimental results demonstrate the usefulness of the proposed methodology and suggest that cell replication should be an integral part of the physical design flow complementing traditional gate sizing techniques.

Placement driven retiming with a coupled edge timing model

Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear whether the predicted performance improvement will still be valid after placement has been performed. This paper presents a new retiming algorithm using a highly accurate timing model taking into account the effect of retiming on capacitive loads of single wires as well as fanout systems. We propose the integration of retiming into a timing-driven standard cell placement environment based on simulated annealing. Retiming is used as an optimization technique throughout the whole placement process. The experimental results show the benefit of the proposed approach. In comparison with the conventional design flow based on standard FEAS (Leiserson and Saxe, J. VLSI and Computer Sys., pp. 41-67, 1983; and Algorithmica vol. 6, no 1, pp. 5-35, 1991.), our approach achieved an improvement in cycle time of up to 34% and 17% on the average.

Improving Placement under the Constant Delay Model

In this paper, we show that under the constant delay model the placement problem is equivalent to minimizing a weighted sum of wire lengths. The weights can be efficiently computed once in advance and still accurately reflect the circuit area throughout the placement process. The existence of an efficient and accurate cost function allows us to directly optimize circuit area. This leads to better results compared to heuristic edge weight estimates or optimization for secondary criteria such as wire length. We leverage this property to improve a recursive partitioning based tool flow. We achieve area savings of 27% for some circuits and 15% on average. The use of the constant delay model additionally enables timing closure without iterations.

Tight coupling of timing-driven placement and retiming

Retiming is a widely investigated technique for performance optimization. In general, it performs extensive modifications on a circuit netlist, leaving it unclear whether the achieved performance improvement will still be valid after placement has been performed. This paper presents an approach for integrating retiming into a timing-driven placement environment. The experimental results show the benefit of the proposed approach on circuit performance in comparison with design flows using retiming only as a pre- or post-placement optimization method.

Layout driven retiming using the coupled edge timing model

Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear whether the predicted performance improvement is still valid after placement has been performed. This paper presents a new retiming algorithm using a highly accurate timing model. It takes into account the effect of retiming on capacitive loads of single wires as well as fanout systems. Further, we propose the integration of retiming into a timing-driven standard cell placement environment. Retiming is used as an optimization technique throughout the whole placement process. The experimental results show the benefit of the proposed approach. In comparison with the conventional design flow based on the standard FEAS algorithm, our approach achieved an improvement in cycle time of up to 34% and 17% on the average.

Cycle time optimization by timing driven placement with simultaneous netlist transformations

We present new concepts to integrate logic synthesis and physical design. Our methodology uses general Boolean transformations as known from technology-independent synthesis, and a recursive bi-partitioning placement algorithm. In each partitioning step, the precision of the layout data increases. This allows effective guidance of the logic synthesis operations for cycle time optimization. An additional advantage of our approach is that no complicated layout corrections are needed when the netlist is changed.

Layout driven optimization of datapath circuits using arithmetic reasoning

This paper proposes a new formalism for layout-driven optimization of datapaths. It is based on preserving an arithmetic bit level representation of the arithmetic circuit portions throughout various design stages. The arithmetic bit level description takes into account the arithmetic nature of the datapath and facilitates arithmetic reasoning to identify circuit transformations that are too complex to derive for Boolean reasoning. It is a bit-level representation so that it integrates well into standard design flows. Based on this representation, we developed an optimization algorithm for cycle time. It takes interconnect delay into account and can be applied at late design stages. A prototype has been integrated into a commercial EDA environment. For circuits implementing complex arithmetic expressions we achieved performance improvements of up to 32%.

Accelerating retiming under the coupled-edge timing model

Retiming has been shown to be a powerful technique for improving the performance of synchronous circuits. However, even though retiming algorithms of polynomial time complexity have been developed the runtimes still may become prohibitively long for large circuits. For the original FEAS algorithm proposed by Leiserson and Saxe (1983,1991), acceleration techniques have been developed solving this problem in practice. However, FEAS uses a simple circuit model being fairly inaccurate for gate level net lists mapped onto actual technologies. Recently a retiming algorithm FEAS/spl I.bar/CTM based on a new timing model tackling this problem has been proposed. In this paper we present a technique for speeding up execution time of FEAS/spl I.bar/CTM. This technique is also suitable for a variety of published algorithms based on the circuit model proposed by Soyata and Friedman (1994,1997). In this work the approach has been integrated into FEAS/spl I.bar/CTM and its benefit has been proven by experimental results.

Timing driven cell replication during placement for cycle time optimization

This paper presents a new timing driven approach for cell replication tailored to the practical needs of standard cell layout design. Cell replication methods have been studied extensively in the context of generic partitioning problems. However, until now it has remained unclear what practical benefit can be obtained from this concept in a realistic environment for timing-driven layout synthesis. Therfore, this paper presents a timing-driven cell replication procedure, demonstrates its incorporation into a standard cell placement and routing tool and, for the first time, examines its benefit on the final circuit performance in comparison with conventional gate- or transistor-sizing techniques. The proposed method relies on recursively duplicating cells located on timing-critical paths. Cell duplications are selected with the objective to reduce the length of the critical nets as well as to simplify the routing task for these nets. Additionally, the fanout load of a cell driving such a net is reduced. Experimental results demonstrate the usefulness of the proposed methodology and suggest that cell replication should be an integral part of the physical design flow complementing traditional gate sizing techniques.