Michel R. C. M. Berkelaar

Gate sizing using a statistical delay model

This paper is about gate sizing under a statistical delay model. It shows we can solve the gate sizing problem exactly for a given statistical delay model. The formulation used allows many different forms of objective functions, which could for example directly optimize the delay uncertainty at the circuit outputs. We formulate the gate sizing problem as a nonlinear programming problem, and show that if we do this carefully, we can solve these problems exactly for circuits up to a few thousand gates using the publicly available large scale nonlinear programming solver LANCELOT.

Technology mapping for standard-cell generators

A novel approach to technology mapping that produces a standard-cell IC implementation from a previously optimized and decomposed set of Boolean functions is presented. Instead of trying to solve the problem for random libraries of standard cells, which proved to be very difficult, it has been solved for cell generators, which are only limited by technology constraints. The completeness of the sets of cells that can be generated by a cell generator, given a certain technology, makes it possible to use an elegant mapping algorithm. The algorithm was coded in CommonLISP, and used to map a large number of benchmark examples. The results compare favorably with published results.<<ETX>>

Efficient orthonormality testing for synthesis with pass-transistor selectors

This paper presents the mapping problem for pass transistor selector mapping, which has not been addressed before. Pass transistor synthesis is potentially important for semi- or full-custom design techniques, which are increasingly attracting attention. Pass transistors have the advantage that fewer transistors are needed, and that circuits with high fanin and small delay can be constructed. Technology mapping approaches in the existing literature cannot handle these selectors, due to the restriction of I-hot encoding of the control signals. We present a new algorithm to address this problem, which is based an the novel idea of a general Boolean Oracle. Our oracle is based on ATPG techniques, and compared to BDDs, the oracle has the advantage that failure to complete only affects optimization locally, and does not hinder optimization elsewhere in the logic. A limitation of BDDs is that it is difficult to complete the algorithm if a BDD grows too large. The experimental results show up to 82% improvement in transistor count for the MCNC combinatorial multi-level examples.

Real area-power-delay trade-off in EUCLID logic synthesis system

The EUCLID logic synthesis system, in which true area-power-delay trade-off is possible, is described. To achieve this, area, delay, and power consumption are estimated at every stage of the process, and optimization decisions taken accordingly. Optimal gate-sizing fine tunes the delay of the circuit, EUCLID provides a framework to explore the area-delay-power design space for a given circuit, giving the designer an optimal implementation based on design needs. Currently, EUCLID is able to handle circuits of several thousands of transistors, with each tool running in a few minutes. Smaller circuits, with smaller hundreds of transistors, only take seconds to run.<<ETX>>

Efficient exact and heuristic minimization of hazard-free logic

In this paper we consider the problem of finding minimum and minimal sum of product circuits (PLAs) that correctly implement a given set of transitions without any hazards. In earlier work we introduced an efficient divide and conquer algorithm, the threeway method, that is capable of finding a minimum PLA-implementation for single output functions. We showed that this method was 10 times faster than the exact method proposed by Dill/Nowick. In this paper we extend the threeway method such that it can deal with multiple output functions. We compare the enhanced threeway method again with Dill/Nowicks method. We also propose an efficient heuristic method, derived from the threeway method, that is capable of finding minimal implementations of specifications that cannot be minimized by the exact methods.

An efficient divide and conquer algorithm for exact hazard free logic minimization

In this paper we introduce the first divide and conquer algorithm that is capable of exact hazard-free logic minimization in a constructive way. We compare our algorithm with the method of Dill and Nowick (1992), which was the only known method for exact hazard-free minimization. We show that our algorithm is much faster than the method proposed by Dill and Nowick by avoiding a significant part of the search space. We argue that the proposed algorithm is a promising framework for the development of efficient heuristic algorithms.