Ingrid B. Peterson

Identifying Process Window marginalities of reticle designs for 0.15/0.13 μm technologies

The complexity of Resolution Enhancements Techniques (RET) will increase dramatically in the next four generations of optical lithography, requiring careful qualification of new reticle designs when they arrive at the wafer fab and before commiting them to printing product. Low k1 and high MEF lithography increase the printability and frequency of yield impacting repeating defects from reticle defects and RET layout errors. Therefore, reticle qualification must include qualifying the reticles for mask processing errors as well as for RET design rule violations. The former is performed on a reticle inspection tool and the latter on a wafer inspection tool after printing wafers with a specific layout using the reticles of interest. The output from the wafer inspection tool followed by detailed analysis provides information on the regions of marginality within the reticle field or features within the die which have smaller process window than expected. We call this the Process Window Qualification Output, PWQ Output and it can be applied to single and multi-die reticle designs. Once these locations are identified by PWQ and the features are determined to be critical to the functionality of the device, further process window analysis on the CD SEM is performed to identify if sufficient process window overlap exists between these features and all other critical features in the device. If the process window overlap of the marginal features with other critical features is acceptable, the reticle can be used to print product. These marginal regions are then carefully monitored on product by CD Metrology. If insufficient overlap in the process windows is found, the PWQ Output features are overlayed with the CAD design and a design fix might be required, followed by the manufacturing of a new reticle. In this paper we describe how we used the PWQ methodology to identify RET design errors for three different reticle designs; in the first example, the marginal feature is an OPC sizing error causing the below design rule spacing in a 0.13μm Gate reticle design to bridge within the process window and the second example is that of a marginal feature associated with improper biasing and a phase error for an Attenuated PSM reticle. The final example shows how PWQ was used to verify the printing of an assist feature within the process window for a Gate 0.13μm reticle.

Process-window sensitive full-chip inspection for design-to-silicon optimization in the sub-wavelength era

As lithographers continue to implement more exotic and complex Resolution Enhancement Techniques (RET) to push patterning further beyond the physical limits of optical lithography, full-chip brightfield inspections are be-coming increasingly valuable to help identify random and systematic defects that occur due to mask tolerance ex-cursions, OPC inaccuracies, RET design errors, or unmanufacturable layout configurations. PWQ, or Process Window Qualification, is a KLA-Tencor product* using brightfield imaging inspection technology that has been developed to address the need for rapid full-chip process window verification. PWQ is currently implemented at IBM’s 300mm facility and is being used to isolate features that repeatedly fail as a function of exposure dose and focus errors. We will demonstrate how PWQ results have assisted in: 1) qualification of reticles and new OPC models; 2) identification of non-obvious lithographic features that limit common process windows; 3) providing input for long-term design for manufacturability (DfM), OPC, and/or RET modeling. PWQ allows full or partial chips to be scanned in far less time than a multi-point common process window collected on a SEM. PWQ findings supplement these traditional analysis methods by encompassing all features on a chip, providing more detail on where the process window truly lies. Examples of marginal features that were detected by PWQ methods and their subsequent actions will be discussed in this paper for an advanced 65nm and a 90nm CMOS process.

Defect reduction methodology in the lithography module

One of the challenges facing the implementation of DUV and advanced in-line lithography processes in production is that of maintaining low defect density in order to minimize the impact on yield. Yield depends on the complex interaction between design, CD and overlay control, films, electrical parameters. As the geometries shrink and the chip size increase, defect reduction becomes increasingly important. Defect density is just as important as critical dimension and overlay metrology in the development and implementation of lithography processes. Achieving and maintaining low- defect density lithography processes necessary for sub- quarter micron technologies requires a defect reduction methodology that quickly detects critical defects, reduces yield-limiting excursions and minimizes cost. This methodology encompasses test and product-wafer inspections combined with a careful selection of the defect inspection tool. Automated Defect Classification cuts the time to results: it facilitates defect source isolation and excursion control enabling an easy implementation of SPC limits by critical defect types. A sampling strategy that balances the cost due to inspection vs. cost due to defect excursions is required.

Successful demonstration of a comprehensive lithography defect monitoring strategy

This paper describes the validation of the methodology, the model and the impact of an optimized Lithography Defect Monitoring Strategy at two different semiconductor manufacturing factories. The lithography defect inspection optimization was implemented for the Gate Module at both factories running 0.13-0.15μm technologies on 200mm wafers, one running microprocessor and the other memory devices. As minimum dimensions and process windows decrease in the lithography area, new technologies and technological advances with resists and resist systems are being implemented to meet the demands. Along with these new technological advances in the lithography area comes potentially unforeseen defect issues. The latest lithography processes involve new resists in extremely thin, uniform films, exposing the films under conditions of highly optimized focus and illumination, and finally removing the resist completely and cleanly. The lithography cell is defined as the cluster of process equipment that accomplishes the coating process (surface prep, resist spin, edge-bead removal and soft bake), the alignment and exposure, and the developing process (post-exposure bake, develop, rinse) of the resist. Often the resist spinning process involves multiple materials such as BARC (bottom ARC) and / or TARC (top ARC) materials in addition to the resist itself. The introduction of these new materials with the multiple materials interfaces and the tightness of the process windows leads to an increased variety of defect mechanisms in the lithography area. Defect management in the lithography area has become critical to successful product introduction and yield ramp. The semiconductor process itself contributes the largest number and variety of defects, and a significant portion of the total defects originate within the lithography cell. From a defect management perspective, the lithography cell has some unique characteristics. First, defects in the lithography process module have the widest range of sizes, from full-wafer to suboptical, and with the largest variety of characteristics. Some of these defects fall into the categories of coating problems, focus and exposure defects, developer defects, edge-bead removal problems, contamination and scratches usually defined as lithography macro defects as shown in Figure 1. Others fall into the category of lithography micro defects, Figure 2. They are characterized as having low topography such as stains, developer spots, satellites, are very small such as micro-bridging, partial micro-bridging, micro-bubbles, CD variation and single isolated missing or deformed contacts or vias. Lithography is the only area of the fab besides CMP in which defect excursions can be corrected by reworking the wafers. The opportunity to fix defect problems without scrapping wafers is best served by a defect inspection strategy that captures the full range of all relevant defect types with a proper balance between the costs of monitoring and inspection and the potential cost of yield loss. In the previous paper [1] it was shown that a combination of macro inspection and high numerical aperture (NA) brightfield imaging inspection technology is best suited for the application in the case of the idealized fab modeled. In this paper we will report on the successful efforts in implementing and validating the lithography defect monitoring strategy at two existing 200 mm factories running 0.15 μm and 0.13 μm design rules.

Investigation of fast and accurate reticle defect assessment methods using STARlight for chrome-on-glass reticle defects

Fast and accurate reticle defect assessment becomes increasingly important because wafer critical dimensions continue to shrink and mask inspection equipment has moved into the UV range thereby increasing the number of detected reticle defects. Defect size is not sufficient in determining if a defect prints or does not print and the threshold size for printing defects can vary broadly between 0.35 (lambda) /NA. At the low k1 factors required to print current technology feature sizes, correlation between reticle and wafer CDs ceases to be linear. The impact of reticle defects on CDs therefore, is more critical than for previous technologies and defect size, shape, and proximity to other features must be taken into consideration. Presented in this paper is an evaluation of different methods to determine the accuracy of imaging prediction for reticle defects, decreasing the time to results in a prediction environment by accelerating the decision process. These methods include printability based on aerial image and the in-line STARlight Contamination Printability Index.