Ingrid E. Magdo

Vertical p-n-p for complementary bipolar technology

A process to fabricate high-performance vertical p-n-p devices has been developed. The use of a high-dose boron-implanted poly-Si layer to form the emitter is essential to obtain shallow emitters with high emitter gradient. The devices exhibit very high current gain (>200) and a calculated cutoff frequency of 3.6 GHz. The process as developed is compatible with the n-p-n process and, thus, suitable for fabrication of complementary bipolar devices.

High-speed transistor with double base diffusion

The general trend in bipolar integrated circuits is to increase circuit speed. Most present high-speed transistor switching circuits are voltage driven; thus device base resistance plays the most important role in limiting circuit speed.(1) The base resistance R b forms two important time constants, R b C d and (R e /R L ) R b C C′ with the emitter diffusion capacitance, C d′ , and the collector capacitance, C c′ respectively. These two time constants dominate the switching delay of the circuit about equally. Emitter diffusion capacitance is approximately equation where f t is the cut off frequency, and R e is the emitter diode resistance.

A high-performance, low-power 2.5 × 2.5 /im emitter transistor

Power dissipation becomes a limiting factor for large-scale integration. Thus, power must be reduced without degrading circuit performance. Reducing the emitter size and thereby the transistor area enables one to operate a circuit at low power levels without degrading its frequency response. The present state of photolithography, however, sets a lower limit on emitter size, which is approximately 2. 5 × 10 µm. We describe a scheme for fabricating transistors reproducibly with 2.5×2.5 µm emitters with present photolithographic capabilities. This scheme follows conventional processing through base diffusion. However, after base diffusion, the base window is convered with a layer of SiO /SiO 2 /Si 3 N 4 . A 2.5 × 10 µm emitter window is first opened in the Si 3 N 4 layer. A second masking step follows using an emitter pattern of the same size, but rotated 90 degrees to form a cross-pattern. Etching the underlying SiO 2 selectively will result in a 2.5×2.5 µm emitter window. As a result of emitter-size reduction, the current level at which f T peaks has been reduced from 5 to 2 mA. The level for maximum current gain has also been reduced, from 1 mA to 100 µA. The collector-base and emitter-base capacitances have been reduced from 0.11 to 0. 06 pF and from 0.1 to 0. 04 pF, respectively.