Shakir Ahmed Abbas

Substrate current-a device and process monitor

Typical characteristics of an n-channel, enhancement-mode, insulated-gate field effect transistor (IGFET) are shown in Figure 1. The drain current is plotted against the drain voltage for different values of the gate voltage. It can be seen from the figure that, after saturation is reached, the drain current increases again as the drain voltage is further increased. This additional current is attributed to the substrate current and can be measured simultaneously in the substrate lead.

Low-leakage, N-channel silicon gate FET with a self-aligned field shield

This paper describes a low leakage n-channel Si gate FET. An n-doped polycrystalline Si field shield was used to achieve low junction leakage. Field shield and diffusion self-alignment was obtained by using a nitride-oxide insulator between the shield and the substrate. A gated diode structure and charge retention cell were used to characterize junction leakage. A -0.5 to -1.0 volt shield-to-substrate bias produced minimum junction leakage. Average minimum leakage, measured at 25°C and 9 volts reverse bias, was 6.5\times10^{-15} A/mil2; corresponding retention time of a charge retention cell was 158 sec. 300A SiO 2 plus 300A Si 3 N 4 was used for the gate dielectric. The silicon gate was dopea during the POCl 3 source-drain diffusion process. Average threshold voltage was 0.88 volts (at V SX = -3V); average normalized transconductance, 36.1 micromhos/volt, corresponds to an effective mobility of 525 cm2/V-sec. Devices made with a nitride-oxide gate insulator can exhibit a large threshold voltage shift when stressed at elevated temperatures. This shift is caused by the differential conductivity mechanism. The V t shift is greatly reduced by annealing the Si 3 N 4 for 1 hr. in steam at 1000°C prior to silicon gate deposition. This anneal reduces the V t shift from greater than 1V to less than 100mV for devices stressed at 14V, 165°C, and 500 hr.