Iñigo Ugarte

Functional vector generation for assertion-based verification at behavioral level using interval analysis

The 2001 International Technology Roadmap for Semiconductors (ITRS) predicts that it is unlikely that verification will be manageable for designs envisioned beyond 2007 without design-for-verifiability. Some CAD vendors have promoted assertion-based verification (ABV) as one of the first commercial design-for-verification techniques. In order to handle complex design, this methodology has to be complemented with tools that automatically generate vectors or counterexamples that violate/verify proposed assertions or constraints. This paper presents an assertion checking technique for behavioral models that combines a non-linear solver and state exploration techniques and avoids expanding behavior into logic equations. The kernel of the technique is a modified interval analysis (MODIA) that avoids most of the problems of classical interval analysis (IA) and improves reuse during vector generation. The results show that the proposed technique is able to handle very efficiently data-dominated designs, which research and commercial assertion/property checkers are unable or need more CPU effort to verify.

Formal meaning of coverage metrics in simulation-based hardware design verification

As the latest version of the International Technology Roadmap for Semiconductors highlights, verification has become the dominant cost of the electronic system design process. Although advances in formal methods have improved some aspects of the task, software simulation remains the primary method of functional verification. Traditionally, heuristic coverage metrics have been used to evaluate the simulation-based validation process and the development of coverage-driven random-based test bench generation techniques is allowing the automation of the functional verification process. This coverage-based approach has a very serious disadvantage: the metrics have no formal meaning and so there is no direct correlation between classes of bugs and coverage metrics. The main goal of this paper is to explore methods that provide a formal meaning to coverage metrics with random test benches. They are independent of a particular fault or bug model. The methods are based on polynomial models of the system under verification and they can evaluate data and control statements.

Assertion checking of behavioral descriptions with nonlinear solver

Verification has become the major bottleneck of the design process. According to the latest report of the International Technology Roadmap for Semiconductors, the challenge is to develop new design-for-verifiability techniques and verification methods for higher levels of abstraction. Several design-for-verifiability methodologies (DFV) have been proposed and assertion-based verification (ABV) is one of the most promising. In order to automatically verify assertions at the higher abstraction levels, it is necessary to improve the performances and capabilities of current constraint solvers. This paper presents a new technique based on nonlinear solvers that automatically checks assertions in behavioral descriptions of hardware systems. These descriptions are modeled with a set of integer polynomial inequalities. The technique provides better results than SAT solvers and it is applied to real designs, such as Viterbi decoders or vocoder digital filters.

Assertion-based Verification of Behavioral Descriptions with Non-linear Solver

Verification has become the major bottleneck of the design process. According to the latest report of the International Technology Roadmap for Semiconductors, the challenge is to develop new design-for-verifiability techniques and verification methods for higher levels of abstraction. Several design-for-verifiability methodologies (DFV) have been proposed and assertion-based verification (ABV) is one of the most promising. In order to automatically verify assertions at the higher abstraction levels, it is necessary to improve the performances and capabilities of current constraint solvers. This paper presents a new technique based on non-linear solvers that automatically checks assertions in behavioral descriptions of hardware systems. These descriptions are modeled with a set of integer polynomial inequalities. These techniques have been verified with several control dominated modules of an MPEG decoder and with data dominated designs, such as Viterbi decoders or vocoder digital filters

Specification components: reusability at the HW/SW system specification level

Reusability at the system specification level is analyzed. By system specification, we mean the executable specification used as input for the HW/SW co-design process. The macros to be reused in different applications are called specification components. They have a wider reusability than the RT-level soft macros used currently as they can be reused in a larger number of different applications with very different design constraints in terms of performance, cost, power consumption, etc. Moreover, their adaptability to new technologies and or design approaches is maximal. The design-for-reuse constraints for these kinds of blocks are discussed. A system specification example is presented with the aim of demonstrating the proposed embedded system design-for-reuse methodology.

Concurrent Specification of Embedded Systems: An Insight into the Flexibility vs Correctness Trade-Off

In 2002, (Kish, 2002) warned about the danger of the abrupt break in Moore’s law. Fortunately, nowadays integration capabilities are still growing and 20nm and 14nm technologies are envisaged, (Chiang, 2011). However, the frequency of integrated circuits cannot grow anymore. Therefore, in order to achieve a continuous improvement of performance, computer architectures are evolving towards the integration of more and more parallel computing resources. Examples of this include modern Graphical Processing Units (GPUs), such as the new CUDA architecture, named Fermi, which will use 512 cores, (Halfhill, 2012). Embedded system architectures show a similar trend with General Purpose Processors (GPPs), and some mobile phones already included between 2 and 8 RISC processors a few years ago, (Martin, 2006). Moreover, many embedded architectures are heterogeneous, and enclose different types of truly parallel computing resources such as (GPPs), Co-Processors, Digital Signal Processors, GPUs, custom-hardware accelerators, etc.

HW-SW codesign of a positioning system. From UML to implementation case study

During the last years, there has been a growing interest in systems related to the location of objects into three-dimensional environments and virtual reality applications. These systems, based on high-performance video-processing, have a big computational load, specially on image analysis phases. This work presents the process of HW-SW co-design and implementation of a positioning system. A methodology was applied in which the requirements and initial functionality was captured in UML-MARTE. After a high-level profiling of the system, an acceleration of most time-demanding stages is achieved by combining the hardware and software capabilities of Zynq platform targeting a low power embedded system. The performance obtained through hardware acceleration of critical parts of the application leads to a significant improvement in the throughput of the whole system. On the other hand, the presented work can also be seen as a proof of concept of the followed methodology.

Affordable, easy-to-use robotic arm used in hardware description languages teaching

Practical activities are critical teaching mechanisms since they enable the acquisition of professional competences while involving and motivating the students. Thus, it is necessary to organize realistic and sufficiently complex activities that, at the same time, can be easily understood and correctly performed by the students. In this context the disposal of physical systems that enables students to interact with the real world are very interesting. However, limitations in the cost and complexity of the systems can present problems. To overcome these limitations, the paper presents an affordable robotic arm that has been used to support the teaching of VHDL language to students of the second-year Telecommunications degree. As a result, students have been able to design, simulate and implement different components creating a final, real system with a motivating practical result.

Optimized coverage-directed random simulation

Due to the growing complexity of modern digital systems, functional verification is still an important challenge. Current verification practice in industry and in academia includes simulation and formal techniques. While formal tools can handle small to medium size designs, only simulation-based tools can validate digital systems of almost infinite complexity. One of the main disadvantages of simulation is that only one set of behaviors is explored. In order to improve simulation, several coverage metrics have been proposed. These metrics (such as line, path or conditional coverage) provide information about the variety of behavior that a particular test-bench explores. With modern digital systems, it is difficult to obtain high coverage, thus a key challenge, according to the latest report of the ITRS, is to create new solutions that can provide high coverage at all hierarchical levels of a design. Verification plans commonly use random test bench generation. However, this technique normally provides a low coverage that is not improved by increasing the number of test-benches. The main contribution of this paper is the development of a behavioral verification technique that enables the improvement of the coverage of random test-benches. The algorithm takes advantage of the structure of the behavioral system description and the information that the simulation produces.

Extended abstract: polynomial model-based evaluation of the branch coverage metric for functional verification of hardware systems

As the latest version of the International Technology Roadmap for Semiconductor (ITRS) highlights, verification has become the dominant cost of the electronic system design process. Although advances in formal methods have improved some aspects of the task, software simulation remains the primary method of functional verification. Traditionally, heuristic coverage metrics have been used to evaluate the simulation-based verification process. This coverage-based approach has a very serious disadvantage: the metrics have no formal meaning and so there is no direct correlation between classes of bugs and coverage metrics. The main goal of this paper is to explore methods that provide a formal meaning to branch coverage with random test benches. The methods are based on polynomial models of the system under verification and they are independent of a particular fault model.