Fernando Herrera

Systematic embedded software generation from SystemC

The embedded software design cost represents an important percentage of the embedded-system development costs [1]. This paper presents a method for systematic embedded software generation that reduces the software generation cost in a platform-based HW/SW codesign methodology for embedded systems based on SystemC. The goal is that the same SystemC code allows system-level specification and verification, and, after SW/HW partition, SW/HW co-simulation and embedded software generation. The C++ code for the SW partition (processes and process communication including HW/SW interfaces) is systematically generated including the user-selected embedded OS (e.g.: the eCos open source OS).

A framework for heterogeneous specification and design of electronic embedded systems in SystemC

This work proposes a methodology which enables heterogeneous specification of complex, electronic systems in SystemC supporting the integration of components under different models of computation (MoCs). This feature is necessary in order to deal with the growing complexity, concurrency, and heterogeneity of electronic embedded systems. The specification methodology is based on the SystemC standard language. Nevertheless, the use of SystemC for heterogeneous system specification is not straightforward. The first problem to be addressed is the efficient and predictable mapping of untimed events required by abstract MoCs over the discrete-event MoC on which the SystemC simulation kernel is based. This mapping is essential in order to understand the simulation results provided by the SystemC model of those MoCs. The specification methodology proposes the set of rules and guidelines required by each specific MoC. Moreover, the methodology supports a smooth integration of several MoCs in the same system specification. A set of facilities is provided covering the deficiencies of the language. These facilities constitute the methodology-specific library called HetSC. The methodology and associated library have been demonstrated to be useful for the specification of complex, heterogeneous embedded systems supporting essential design tasks such as performance analysis and SW generation.

System-level performance analysis in SystemC

As both the ITRS and the Medea+ DA Roadmaps have highlighted, early performance estimation is an essential step in any SoC design methodology based on International Technology Roadmap for Semiconductors (2001) and The MEDEA+ Design Automation Roadmap (2002). This paper presents a C++ library for timing estimation at system level. The library is based on a general and systematic methodology that takes as input the original SystemC source code without any modification and provides the estimation parameters by simply including the library within a usual simulation. As a consequence, the same models of computation used during system design are preserved and all simulation conditions are maintained. The method exploits the advantages of dynamic analysis, that is, easy management of unpredictable data-dependent conditions and computational efficiency compared with other alternatives (ISS or RT simulation, without the need for SW generation and compilation and HW synthesis). Results obtained on several examples show the accuracy of the method. In addition to the fundamental parameters needed for system-level design exploration, the proposed methodology allows the designer to include capture points at any place in the code. The user can process the corresponding captured events for unrestricted timing constraint verification.

A framework for embedded system specification under different models of computation in SystemC

This paper presents a heterogeneous specification methodology built on top of the standard SystemC kernel. The methodology enables abstract specification supporting heterogeneity, which in this context entails the ability to describe and connect parts of the system specification under different models of computation (MoCs). A main and distinguishing contribution of the methodology is that the support is provided while maintaining the standard kernel of SystemC unchanged, by means of a set of specification rules and a heterogeneous support library built on top of the SystemC standard library. This is possible thanks to an abstraction technique that can integrate any new MoC that can be abstracted over the underlying discrete-event simulation kernel. Primitives, guidelines and rules of the specification methodology, including those related to heterogeneous support, and the basis of the abstraction technique are described. Experimental results demonstrate the benefits of the methodology

The COMPLEX methodology for UML/MARTE Modeling and design space exploration of embedded systems

The design of embedded systems is being challenged by their growing complexity and tight performance requirements. This paper presents the COMPLEX UML/MARTE Design Space Exploration methodology, an approach based on a novel combination of Model Driven Engineering (MDE), Electronic System Level (ESL) and design exploration technologies. The proposed framework enables capturing the set of possible design solutions, that is, the design space, in an abstract, standard and graphical way by relying on UML and the standard MARTE profile. From that UML/MARTE based model, the automated generation framework proposed produces an executable, configurable and fast performance model which includes functional code of the application components. This generated model integrates an XML-based interface for communication with the tool which steers the exploration. This way, the DSE loop iterations are efficiently performed, without user intervention, avoiding slow manual editions, or regeneration of the performance model. The novel DSE suited modelling features of the methodology are shown in detail. The paper also presents the performance model generation framework, including the enhancements with regard the previous simulation and estimation technology, and the exploration technology. The paper uses an EFR vocoder system example for showing the methodology and for demonstrative results.

The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration

The consideration of an embedded devices power consumption and its management is increasingly important nowadays. Currently, it is not easily possible to integrate power information already during the platform exploration phase. In this paper, we discuss the design challenges of todays heterogeneous HW/SW systems regarding power and complexity, both for platform vendors as well as system integrators. As a result, we propose a reference framework and design flow concept that combines system-level power optimization techniques with platform-based rapid prototyping. Virtual executable prototypes are generated from MARTE/UML and functional C/C++ descriptions, which then allows to study different platforms, mapping alternatives, and power management strategies. Our proposed flow combines system-level timing and power estimation techniques available in commercial tools with platform-based rapid prototyping. We propose an efficient code annotation technique for timing and power properties enabling fast host execution as well as adaptive collection of power traces. Combined with a flexible design-space exploration (DSE) approach our flow allows a trade-off analysis between different platforms, mapping alternatives, and optimization techniques, based on domain-specific workload scenarios. The proposed framework and design flow has been implemented in the COMPLEX FP7 European integrated project.

Single Source Design Environment for Embedded Systems Based on SystemC

There is a clear need for new methodologies supporting efficient design of embedded systems on complex platforms implementing both hardware and software modules. Software development has to be carried out under a closer relationship with the underlying platform. The current trend is towards an increasing embedded software development effort under more stringent time-to-market requirements. As a consequence, it is necessary to reduce software generation cost while maintaining reliability and design quality.In that context, languages centered on describing whole systems, with software and hardware parts, have been proposed. Among these, SystemC is gaining increasing interest as a specification language for embedded systems. SystemC supports the specification of the complete system and the modeling of the platform. In this paper, the application of SystemC to performance analysis and embedded software generation is discussed. A single-source approach is proposed, that is, the use of the same code for system-level specification and profiling, and, after architectural mapping, for HW/SW co-simulation and embedded software generation. A design environment based on C++ libraries for performance analysis and software generation is presented. This approach avoids working on intermediate formats and translators, which facilitates the designer’s interaction with the system description throughout the development process. Additionally, it ensures the preservation of the computational models used for the system specification during architectural mapping and compilation.

A MDD methodology for specification of embedded systems and automatic generation of fast configurable and executable performance models

This paper presents the COMPLEX UML/MARTE modeling methodology and its related framework for automatic generation of executable performance models. The modeling methodology supports Model-Driven Development (MDD), required by industrial flows, and a novel set of modeling features specifically suitable for Design Space Exploration (DSE), a crucial design activity. The COMPLEX framework has other advantages for DSE. The COMPLEX tooling enables the automatic generation of an executable and configurable model for fast performance analysis without requiring engineering effort. The COMPLEX tooling automates the production of an easily portable text-based representation of the UML/MARTE model. This representation is read by the underlying simulation infrastructure, which automatically builds a fast performance model supporting the evaluation of different configurations of the system. An important aspect of this performance analysis framework is that it supports a system-level text-based front-end, which is produced from the COMPLEX UML/MARTE model, and which avoids the development of SW implementations, HW refinements, or the implementation of HW/SW interfaces. Moreover, neither code regeneration, nor recompilation is required for any DSE iterations, and thus, the time taken in the exploration is mostly due to model simulation.

The Andres Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems

Todays heterogeneous embedded systems combine components from different domains, such as software, analogue hardware and digital hardware. The design and implementation of these systems is still a complex and error-prone task clue to the different Models of Computations (MoCs), design languages and tools associated with each of the domains. Though making such systems adaptive is technologically feasible, most of the current design methodologies do not explicitely support adaptive architectures. This paper present the ANDRES project. The main objective of ANDRES is the development of a seamless design flow for adaptive heterogeneous embedded systems (AHES) based on the modelling language SystemC. Using domain-specific modelling extensions and libraries, ANDRES will provide means to efficiently use and exploit adaptivity in embedded system design. The design flow is completed by a methodology and tools for automatic hardware and software synthesis for adaptive architectures.

Enhanced IP-XACT Platform Descriptions for Automatic Generation from UML/MARTE of Fast Performance Models for DSE

This paper presents a framework which, starting from a UML/MARTE model of the embedded system, relies on an enhanced IP-XACT description of the platform for the automatic generation of fast performance executable models. The IP-XACT description of the HW architecture is automatically generated from the UML/MARTE model. The enhancement proposed extends the current capabilities of the IP-XACT standard in order to add semantic information to the HW architecture and to support the integration of Hardware Dependent Software (HdS). This way, HW and SW aspects of the integration of a component in a virtual platform model are covered. The applicability of the proposed extensions is shown by supporting the proposed IP-XACT descriptions at the front-end of a simulation infrastructure suited for fast performance assessment, and for supporting design space exploration.