Víctor Fernández

Partial scan high-level synthesis

Classical strategies in design for testability are applied at the gate-level, after the RT-logic synthesis process. New techniques covering test and synthesis (Test Synthesis) are appearing but their application is mainly oriented to gate level (commercial tools such as Synopsys). On the other hand, most high-level synthesis tools do not take into account the testability of the final architecture. This paper presents a high-level synthesis system which includes testability improvement among its goals. The aforementioned system generates loop free circuits and are therefore, easily testable with partial scan techniques. In order to achieve this, a complete RT-level loop classification is made and the origin at the algorithmic level is analyzed in order to avoid loops during the synthesis process, not only in the data path but also in the controller. With the usual high-level synthesis benchmarks, the proposed system reaches 100% fault coverages with a smaller area than other high-level synthesis tools.

Single Source Design Environment for Embedded Systems Based on SystemC

There is a clear need for new methodologies supporting efficient design of embedded systems on complex platforms implementing both hardware and software modules. Software development has to be carried out under a closer relationship with the underlying platform. The current trend is towards an increasing embedded software development effort under more stringent time-to-market requirements. As a consequence, it is necessary to reduce software generation cost while maintaining reliability and design quality.In that context, languages centered on describing whole systems, with software and hardware parts, have been proposed. Among these, SystemC is gaining increasing interest as a specification language for embedded systems. SystemC supports the specification of the complete system and the modeling of the platform. In this paper, the application of SystemC to performance analysis and embedded software generation is discussed. A single-source approach is proposed, that is, the use of the same code for system-level specification and profiling, and, after architectural mapping, for HW/SW co-simulation and embedded software generation. A design environment based on C++ libraries for performance analysis and software generation is presented. This approach avoids working on intermediate formats and translators, which facilitates the designer’s interaction with the system description throughout the development process. Additionally, it ensures the preservation of the computational models used for the system specification during architectural mapping and compilation.

Embedded software generation from systemC for platform based design

The current trend in embedded system design is towards an increasing percentage of the embedded SW development cost of the total embedded system design costs. There is a clear need of reducing SW generation cost while maintaining reliability and design quality. SystemC represents a step forward in ensuring these goals. In this chapter, the application of SystemC to embedded SW generation is discussed. The state of art of the existing techniques for SW generation is analyzed and their advantages and drawbacks presented. In addition, methods for systematic embedded software generation which reduce the software generation cost in a platform based HW/SW co-design methodology for embedded systems based on SystemC is presented. SystemC supports a single-source approach, that is, the use of the same code for system level specification and verification, and, after HW/SW partitioning, for HW/SW co-simulation and embedded SW generation.

Fault modeling and injection in vital descriptions

In this paper a fault model for VHDL descriptions following the VITAL guidelines is permitted. Fault injection in the elaborated model of the VHDL descriptions are also going to be presented in tis paper.

SystemC-MDVP modelling of pressure driven microfluidic systems

Systems composed by multiple physical domains (i.e. mechanical, biological, optical, fluidic, etc.) and usually controlled by an embedded HW/SW circuit cannot, up to date, be jointly simulated in order to correctly specify, dimension and verify these multi-domain microelectronics assisted systems at an early system level stage. This paper describes part of the work that it is being carrying out (under the CATRENE CA701 project) in order to define an open framework, based on SystemC-AMS, with the aim to extend this language to support multiple physical domains. The proposed extensions for being able to model a micro-fluidic system are going to be exposed. Two approaches have been selected: to model the fluid analytically based on the Poiseuille flow theory and to model the fluid numerically following the SPH (Smoothed Particle Hydrodynamics) approach. Both modeling techniques are, by now, encapsulated under the TDF (Timed Data Flow) MoC (Model of Computation) of SystemC-AMS.

Test Synthesis of Digital Systems

Since their appearance, in the late fifties, the complexity of integrated digital systems has increased greatly. Gordon Moore predicted, at the beginning of the sixties, that the number of transistors in a chip would double approximately every two years. This law, known as Moore’s law, has been fulfilled since then [Sap84], in fact, the complexity of integrated circuits is now reaching a billion transistors. The development of such complex circuits is possible thanks to the use of a series of methodologies and programs which aid the engineer in all the phases of the design process.

HW-SW codesign of a positioning system. From UML to implementation case study

During the last years, there has been a growing interest in systems related to the location of objects into three-dimensional environments and virtual reality applications. These systems, based on high-performance video-processing, have a big computational load, specially on image analysis phases. This work presents the process of HW-SW co-design and implementation of a positioning system. A methodology was applied in which the requirements and initial functionality was captured in UML-MARTE. After a high-level profiling of the system, an acceleration of most time-demanding stages is achieved by combining the hardware and software capabilities of Zynq platform targeting a low power embedded system. The performance obtained through hardware acceleration of critical parts of the application leads to a significant improvement in the throughput of the whole system. On the other hand, the presented work can also be seen as a proof of concept of the followed methodology.

Affordable, easy-to-use robotic arm used in hardware description languages teaching

Practical activities are critical teaching mechanisms since they enable the acquisition of professional competences while involving and motivating the students. Thus, it is necessary to organize realistic and sufficiently complex activities that, at the same time, can be easily understood and correctly performed by the students. In this context the disposal of physical systems that enables students to interact with the real world are very interesting. However, limitations in the cost and complexity of the systems can present problems. To overcome these limitations, the paper presents an affordable robotic arm that has been used to support the teaching of VHDL language to students of the second-year Telecommunications degree. As a result, students have been able to design, simulate and implement different components creating a final, real system with a motivating practical result.

3GPP2/802.20 RC/QC-LDPC encoding

Rate-Compatible/Quasi-Cyclic LDPC codes are gaining importance because of their tradeoff between performance and simplicity. For these reasons, RC/QC LDPC codes have been included in several recent standards such as 802.20 and 3GPP2. General proposals for hardware encoding of this kind of LDPC codes either consume a lot of area to increase the throughput or are slow-encoding schemes to reduce the area consumption. Some others have to pre-compute a non-sparse generator matrix and store it in memory in order to encode. In contrast, by exploiting the number of null matrices in the mother parity check matrix defined in these standards, this proposal defines a low-cost encoder with high input packet throughput (little time between input frames). Moreover, as the encoding is performed using the original parity check matrix, there is no need to pre-compute or store the dense generation matrix in memory.

Optimizing data-flow graphs with min/max, adding and relational operations

During Electronic System-Level (ESL) design, High-Level Synthesis (HLS) tools normally translate the system description to a Control/Data Flow Graph. At this level, several transformations are performed as early as possible to reduce the number and complexity of the data operations. These preliminary transformations (for example, common sub-expression elimination, constant propagation, etc) are typically applied in algebraic expressions with arithmetic operators. This paper presents preliminary transformations that optimize Data-Flow Graphs with relational, maximum/minimum and arithmetic (addition/subtraction) operations. The proposed techniques produce a significant reduction in the number of operations. HLS tools and even software compilers and symbolic algebra packages are not able to generate similar results. The efficiency of the techniques has been evaluated with several modules of real telecommunications standards and their HW implementations show important area reductions and, sometimes, low impact on latency or critical path.