Ionel Zagan

Methods to Improve the Performances of the Real-Time Operating Systems for Small Microcontrollers

The use of real-time operating systems for small micro controllers creates two major problems. The former refers to the way interruptions must be handled so that deadlines can be complied with. The latter regards the fact that there may be tasks that will not synchronize with events generated by multiple objects such as semaphores, mutexes, messages or interrupts. The present article discusses several solutions to improve the performance of Real Time Operating Systems for small micro controllers and eventually overcome the above-mentioned inconveniences.

Predictable CPU Architecture Designed for Small Real-Time Application - Concept and Theory of Operation

The purpose of this paper is to describe an predictable CPU architecture, based on the five stage pipeline assembly line and a hardware scheduler engine. We aim at developing a fine-grained multithreading implementation, named nMPRA-MT. The new proposed architecture uses replication and remapping techniques for the program counter, the register file, and the pipeline registers and is implemented with a FPGA device. An original implementation of a MIPS processor with thread interleaved pipeline is obtained, using dynamic scheduling of hard real-time tasks and interrupts. In terms of interrupts handling, the architecture uses a particular method consisting of assigning interrupts to tasks, which insures an efficient control for both the context switch, and the system real-time behavior. The originality of the approach resides in the predictability and spatial isolation of the hard real-time tasks, executed every two clock cycles. The nMPRA-MT architecture is enabled by an innovative scheme of predictable scheduling algorithm, without stalling the pipeline assembly line.

Improving the Performances of the nMPRA Processor using a Custom Interrupt Management Scheduling Policy

A quantitative and qualitative increase in production has been obtained in most fields through the development of CPUs and real-time systems based on them. Such is the case in the indu ...

Improving the performance of CPU architectures by reducing the Operating System overhead

The predictable CPU architectures that run hard real-time tasks must be executed with isolation in order to provide a timing-analyzable execution for real-time systems. The present article discusses several solutions to improve the performance of CPU architectures and eventually overcome the Operating Systems overhead inconveniences. This paper focuses on the innovative CPU implementation named nMPRA-MT, designed for small real-time applications. This implementation uses replication and remapping techniques for the program counter, general purpose registers and pipeline registers, enabling multiple threads to share a single pipeline assembly line. In order to increase predictability, the proposed architecture partially removes the hazard situation at the expense of larger execution latency per one instruction.

An Approach of nMPRA Architecture using Hardware Implemented Support for Event Prioritization and Treating

One of the fundamental requirements of real time operating systems is the determinism of executing critical tasks and treating multiple periodic or aperiodic events. The present paper presents the hardware support of the nMPRA processor (Multi Pipeline Register Architecture) dedicated to treating time events, interrupt events and events associated with synchronization and inter-task communication mechanisms. Because in real time systems the treatment of events is a very important aspect, this paper describes both the mechanism implemented in hardware for prioritizing and treating multiple events, and the experimental results obtained using Virtex-7 FPGA circuit. The articles element of originality is the very short response time required in treating and prioritizing events.

Implementation of nMPRA CPU architecture based on preemptive hardware scheduler engine and different scheduling algorithms

Taking into consideration the requirements of real-time embedded systems, the processor scheduler must guarantee a constant scheduling frequency, providing determinism and predictability of tasks execution. The purpose of this study is to implement the nMPRA (multi pipeline register architecture) processor into field-programmable gate array, and to integrate the already existing scheduling methods, thus providing a preemptive schedulability analysis of the proposed architecture based on the pipeline assembly line and hardware scheduler. This study describes a hardware implementation of the real-time scheduler named nHSE (hardware scheduler engine for n tasks) and presents the results obtained using the appropriate schedulability methods used in real-time environments. The scheduling and task switch operations are the main source of non-determinism, being successfully dealt with real-time nMPRA concept, in order to improve the systems functionality. Some mechanisms used for synchronisation and inter-task communication are also taken into consideration.

Schedulability analysis of nMPRA processor based on multithreaded execution

This article presents several solutions meant to improve the performance of CPU architecture and it describes a fine-grained multithreading architecture empowered with a hardware scheduler that uses remapping techniques for the program counter, the register file and the pipeline registers. In this context, our main contribution relates to a custom CPU implementation in order to provide predictability execution for hard real-time tasks. Experimental data obtained during tests is analyzed in order to validate the proposed CPU, based on a fine-grained multithreading architecture and a fast switching operation between a blocked task and another one, scheduled by Hardware Scheduler Engine (nHSE). The resource differences between the original Multi Pipeline Register Architecture (nMPRA) implementation and the multithreading configuration are also taken in consideration.

Real-Time Evaluation of nMPRA CPU Architecture Based on Multithreaded Execution

This paper conducts a thorough study of the schedulability and predictability questions for a custom designed CPU architecture, named Multi Pipeline Register Architecture (nMPRA). The nMPRA CPU implementation uses replication and remapping techniques for the program counter, general purpose registers and pipeline registers, providing predictability and hardware-based isolation for hard real-time threads. We describe the real-time scheduling tests on nMPRA processor architecture, including also a fine-grained multithreading configuration. The present paper highlights several solutions to improve the performance of CPU architectures and to overcome the overhead inconveniences of the Operating Systems.

Predictable CPU Architecture Designed for Small Real-Time Applications - Implementation Results

The purpose of this paper is to describe and present the implementation results of nMPRA-MT processor concept designed for small real-time applications. Our target is to validate a fine-grained multithreading CPU architecture that uses replication and remapping techniques for the program counter, general purpose registers and pipeline registers. The new predictable CPU implementation is based on a hardware scheduler engine, being able to schedule dynamically a set of tasks on the five-stage pipeline assembly line. Using a FPGA device from Xilinx, we validate the innovative nMPRA-MT processor, interleaving different types of threads into the pipeline assembly line, providing predictability and hardware-based isolation for hard real-time threads. Mechanisms for synchronization and inter-task communication are also taken into consideration. Keywords— predictable; real-time systems; fine-grained multithreading; hardware scheduler; pipeline; hard real-time