Vasile Gheorghita Gaitan

CPU Architecture Based on a Hardware Scheduler and Independent Pipeline Registers

Task switching, synchronization, and communication between processes are major problems for each real-time operating system. Software implementation of the specific mechanisms may lead to significant delays that can affect deadline requirements for some applications. This paper presents a hardware scheduler architecture integrated into the CPU structure that uses resource remapping techniques for the pipeline registers and for the CPU working registers. We present an original implementation of the hardware structure used for static and dynamic scheduling of the task, unitary management of events, access to architecture shared resources, event generation, and a method used for assigning interrupts to tasks that insures an efficient operation in the context of real-time control. One assembler instruction is used for simultaneous task synchronization with multiple event sources. This architecture allows a task switching time of one clock cycle (with a worst case scenario of three clock cycles for special instructions used for external memory accesses) and a response time of only 1.5 clock cycles for the events. Some mechanisms for improving program execution speed are also taken in consideration.

An RFID and OPC Technology Based Distributed System for Production Control and Monitoring

This paper deals with an implemented system that contains advanced RFID-based control gates and smart connections to an OPC server that acts as central dispatcher. It proposes a scenario focused on the usage of more different control gates together with an integrated solution based on the state of the art industrial technology.

Methods to Improve the Performances of the Real-Time Operating Systems for Small Microcontrollers

The use of real-time operating systems for small micro controllers creates two major problems. The former refers to the way interruptions must be handled so that deadlines can be complied with. The latter regards the fact that there may be tasks that will not synchronize with events generated by multiple objects such as semaphores, mutexes, messages or interrupts. The present article discusses several solutions to improve the performance of Real Time Operating Systems for small micro controllers and eventually overcome the above-mentioned inconveniences.

A Middleware Based Architecture for the Industrial Internet of Things

Due to its potential, the Internet of Things (IoT) begins to be used in the industrial field. Nevertheless, although the concept called the Industrial Internet of Things does not know a widely accepted definition, it is based on the existing technology, and introduces the IoT in the industrial environment through the compliance with specific additional requirements and by integrating various fieldbuses with distinctive features, from the real-time point of view. The aim of this paper is to propose a practical architecture for the Industrial Internet of Things. The proposed architecture is designed around the Data Distribution Service for Real Time System (DDS) middleware protocol, and it is organized on four levels. Between these levels, it is defined standard interface, and they can be developed independently. For this reason, the architecture is scalable because at the middleware level, the DDS can be replaced by other middleware systems. At the final, it is performed a comparison between several middleware systems used in the proposed architecture.

Predictable CPU Architecture Designed for Small Real-Time Application - Concept and Theory of Operation

The purpose of this paper is to describe an predictable CPU architecture, based on the five stage pipeline assembly line and a hardware scheduler engine. We aim at developing a fine-grained multithreading implementation, named nMPRA-MT. The new proposed architecture uses replication and remapping techniques for the program counter, the register file, and the pipeline registers and is implemented with a FPGA device. An original implementation of a MIPS processor with thread interleaved pipeline is obtained, using dynamic scheduling of hard real-time tasks and interrupts. In terms of interrupts handling, the architecture uses a particular method consisting of assigning interrupts to tasks, which insures an efficient control for both the context switch, and the system real-time behavior. The originality of the approach resides in the predictability and spatial isolation of the hard real-time tasks, executed every two clock cycles. The nMPRA-MT architecture is enabled by an innovative scheme of predictable scheduling algorithm, without stalling the pipeline assembly line.

Transparent Interaction of SCADA Systems Developed over Different Technologies

Supervisory control and data acquisition (SCADA) systems are usually distributed applications designed and developed by using a middleware technology. In this paper, it is proposed a solution for interoperability of SCADA systems that are based on different middleware technologies. The proposed solution allows the interconnection of SCADA system based on the following middleware technologies: OPC DA, OPC .NET, OPC UA, TAO (The ACE ORB - an open-source implementation of CORBA standard), and OpenDDS (an open-source implementation of the DDS protocol). The proposed solution is a software application that allows the creation of middleware objects in order to connect to the data servers. In the application framework, it is allowed the interconnection of the tags exposed by the middleware objects (tags are acquired from data servers through a middleware) directly or by a math expression. The proposed solution is scalable in the sense that it can be added new software modules for other types of middleware in addition to those listed above.

Improving interrupt handling in the nMPRA

In the most Real Time Operating Systems (RTOS), the interrupt handlers are implemented in software and they can increase the response time to external events and the overload of the CPU. Therefore, the newest RTOSs implement in hardware the interrupt handlers in order to eliminate these two problems. By analyzing traditional models for the management of interrupts, we can emphasize their inability to provide the temporal determinism required in real-time systems. This paper presents an interrupt handler implemented in hardware based on a method that uses a unified space of priorities for the tasks and interrupts, so there is not a specialized interrupt controller. This solution is integrated in the MPRA (Multi Pipeline Register Architecture) processor that contains a hardware RTOS. The major difference compared to other architectures with hardware scheduler is that the MPRA is a multi-pipeline architecture, which means that each task has its own set of pipeline registers.

An internet of things-based distributed intelligent system with self-optimization for controlling traffic-light intersections

The rapid increase in vehicle fleet size and consequently in traffic volume is not always followed by an increase in road space. As a result, traffic congestion occurs, especially in large urban areas. Therefore, in order to avoid traffic jams, immediate solutions have to be found. Various technologies have been used to design and develop such solutions in the past. While some developers have used classic technologies, others have integrated various emerging technologies in the systems they built in order to make roadways safer. Acting both inside the vehicle and along the roadways the new designed systems are able to inform drivers about traffic conditions and possible hazards. This paper proposes an Internet of Things-based approach to solve some of the problems that traffic congestion raises. Furthermore, this approach provides the means to monitor a set of environmental parameters, including air quality, and to raise early warnings and alarms when critical levels are reached. This approach offers a solution to increasing traffic-related pollution (which has a negative impact on the environment and on peoples health), to economic losses and to other issues caused by traffic congestions. In order to reduce accident risks when various intervention vehicles enter the cross-roads, we also propose a solution based on radio frequency identification (RFID) technology.

Improving the Performances of the nMPRA Processor using a Custom Interrupt Management Scheduling Policy

A quantitative and qualitative increase in production has been obtained in most fields through the development of CPUs and real-time systems based on them. Such is the case in the indu ...

Hardware event treating in nMPRA

In real-time systems, events treating is one of the most important aspects. There can be time events, watchdog timer events, deadline events, interrupt events, mutex events, and synchronization and inter-task communication events. Since multiple events can occur simultaneously, it is important to find a way to select the order in which the events will be treated. For that, in this paper it is presented a method of global prioritization of the events by category using a hardware prioritization scheme for the n-task Multi Pipeline Register Architecture (nMPRA) and an analysis of how are treated mutex and inter-task communication events in the same architecture.