Nicoleta Cristina Gaitan

CPU Architecture Based on a Hardware Scheduler and Independent Pipeline Registers

Task switching, synchronization, and communication between processes are major problems for each real-time operating system. Software implementation of the specific mechanisms may lead to significant delays that can affect deadline requirements for some applications. This paper presents a hardware scheduler architecture integrated into the CPU structure that uses resource remapping techniques for the pipeline registers and for the CPU working registers. We present an original implementation of the hardware structure used for static and dynamic scheduling of the task, unitary management of events, access to architecture shared resources, event generation, and a method used for assigning interrupts to tasks that insures an efficient operation in the context of real-time control. One assembler instruction is used for simultaneous task synchronization with multiple event sources. This architecture allows a task switching time of one clock cycle (with a worst case scenario of three clock cycles for special instructions used for external memory accesses) and a response time of only 1.5 clock cycles for the events. Some mechanisms for improving program execution speed are also taken in consideration.

Methods to Improve the Performances of the Real-Time Operating Systems for Small Microcontrollers

The use of real-time operating systems for small micro controllers creates two major problems. The former refers to the way interruptions must be handled so that deadlines can be complied with. The latter regards the fact that there may be tasks that will not synchronize with events generated by multiple objects such as semaphores, mutexes, messages or interrupts. The present article discusses several solutions to improve the performance of Real Time Operating Systems for small micro controllers and eventually overcome the above-mentioned inconveniences.

A Middleware Based Architecture for the Industrial Internet of Things

Due to its potential, the Internet of Things (IoT) begins to be used in the industrial field. Nevertheless, although the concept called the Industrial Internet of Things does not know a widely accepted definition, it is based on the existing technology, and introduces the IoT in the industrial environment through the compliance with specific additional requirements and by integrating various fieldbuses with distinctive features, from the real-time point of view. The aim of this paper is to propose a practical architecture for the Industrial Internet of Things. The proposed architecture is designed around the Data Distribution Service for Real Time System (DDS) middleware protocol, and it is organized on four levels. Between these levels, it is defined standard interface, and they can be developed independently. For this reason, the architecture is scalable because at the middleware level, the DDS can be replaced by other middleware systems. At the final, it is performed a comparison between several middleware systems used in the proposed architecture.

Predictable CPU Architecture Designed for Small Real-Time Application - Concept and Theory of Operation

The purpose of this paper is to describe an predictable CPU architecture, based on the five stage pipeline assembly line and a hardware scheduler engine. We aim at developing a fine-grained multithreading implementation, named nMPRA-MT. The new proposed architecture uses replication and remapping techniques for the program counter, the register file, and the pipeline registers and is implemented with a FPGA device. An original implementation of a MIPS processor with thread interleaved pipeline is obtained, using dynamic scheduling of hard real-time tasks and interrupts. In terms of interrupts handling, the architecture uses a particular method consisting of assigning interrupts to tasks, which insures an efficient control for both the context switch, and the system real-time behavior. The originality of the approach resides in the predictability and spatial isolation of the hard real-time tasks, executed every two clock cycles. The nMPRA-MT architecture is enabled by an innovative scheme of predictable scheduling algorithm, without stalling the pipeline assembly line.

Transparent Interaction of SCADA Systems Developed over Different Technologies

Supervisory control and data acquisition (SCADA) systems are usually distributed applications designed and developed by using a middleware technology. In this paper, it is proposed a solution for interoperability of SCADA systems that are based on different middleware technologies. The proposed solution allows the interconnection of SCADA system based on the following middleware technologies: OPC DA, OPC .NET, OPC UA, TAO (The ACE ORB - an open-source implementation of CORBA standard), and OpenDDS (an open-source implementation of the DDS protocol). The proposed solution is a software application that allows the creation of middleware objects in order to connect to the data servers. In the application framework, it is allowed the interconnection of the tags exposed by the middleware objects (tags are acquired from data servers through a middleware) directly or by a math expression. The proposed solution is scalable in the sense that it can be added new software modules for other types of middleware in addition to those listed above.

Using Dual Priority scheduling to improve the resource utilization in the nMPRA microcontrollers

The current practice in most of the safety-critical areas, including automotive, avionics systems and factory automation, encouraging the use of real-time time-trigger schedulers that does not allow interference to take place between safety-critical components and non-critical. Furthermore, in these systems the lack of interference between safety-critical components and non-critical components is achieved by a strict isolation between components with different degrees of severity. This approach can assure, easily, the certification of the safety-critical functionality, but leads to very low resource utilization. For this purpose it will be presented a solution that when the system enters into a state that is different from the normal running state (test service), allowing relaxation and a change in the activation time of tasks (release) violating the fixed priorities scheduling, but avoiding starvation of the system tasks. The proposed solution modifies a static scheduler in a dynamic scheduler depending on the system status using Dual Priority scheduling. The algorithm has been proposed to be implemented on a nMPRA processor, by multiplying hardware resources (PC, pipeline registers and file registers) and other facilities (events, mutexes, interrupts, IPC communication, timers, the static scheduler and support for dynamic scheduler) provides a switching and response time for events within 1 to 3 machine cycles.

Improving interrupt handling in the nMPRA

In the most Real Time Operating Systems (RTOS), the interrupt handlers are implemented in software and they can increase the response time to external events and the overload of the CPU. Therefore, the newest RTOSs implement in hardware the interrupt handlers in order to eliminate these two problems. By analyzing traditional models for the management of interrupts, we can emphasize their inability to provide the temporal determinism required in real-time systems. This paper presents an interrupt handler implemented in hardware based on a method that uses a unified space of priorities for the tasks and interrupts, so there is not a specialized interrupt controller. This solution is integrated in the MPRA (Multi Pipeline Register Architecture) processor that contains a hardware RTOS. The major difference compared to other architectures with hardware scheduler is that the MPRA is a multi-pipeline architecture, which means that each task has its own set of pipeline registers.

Monitoring and control system for smart buildings based on OPC UA specifications

The fast development of green buildings that are focused on saving the energy consumption and using the renewable energy resources has led to an accelerated development of solutions for remote monitoring and control of the smart buildings. This is a consequence of the huge market potential for these solutions. This paper presents a solution for monitoring and control of smart buildings based on OPC UA specifications. The system that integrates the MODBUS and BACnet fieldbuses, it can be distributed on the Internet, and it uses the security from the OPC UA specifications based on the security certificates.

MCIP Client Application for SCADA in Iiot Environment

Modern automation systems architectures which include several subsystems for which an adequate burden sharing is required. These subsystems must work together to fulfil the tasks imposed by the common function, given by the business purpose to be fulfilled. These subsystems or components, in order to perform these tasks, must communicate with each other, this being the critical function of the architecture of such a system. This article presents a MCIP (Monitoring and Control of the Industrial Processes) client application which allows the monitoring and control of the industrial processes and which is object-oriented. As a novelty, the paper presents the architecture of the user object, which is actually a wrapper that allows the connection to Communication Standard Interface bus, the characteristics of the IIoT (Industrial Internet of Things) object and the correspondence between a server’s address space and the address space of MCIP.

An Uniform Description Solution for Devices Based on DCON ASCII Protocol

In the developing process of efficient SCADA systems, there can be problems generated due to the field buses diversity, and the devices connected to this field buses. Furthermore, there can be problems encountered at the integration of new devices in the SCADA systems. An effective solution is to use a method that describes these devices so that there is not required to recompile the software module of the SCADA systems. In this paper, it is presented a solution to describe the capabilities of devices based on DCON ASCII protocol. The solution is based on the Electronic Data Sheet (EDS) files that were extended in order to describe the commands, and the answers used to retrieve information for each device. This solution was integrated into a SCADA system that has a modular architecture.