Iouliia Skliarova

Reconfigurable hardware SAT solvers: a survey of systems

By adapting to computations that are not so well-supported by general-purpose processors, reconfigurable systems achieve significant increases in performance. Such computational systems use high-capacity programmable logic devices and are based on processing units customized to the requirements of a particular application. A great deal of the research effort in this area is aimed at accelerating the solution of combinatorial optimization problems. Special attention in this context was given to the Boolean satisfiability (SAT) problem resulting in a considerable number of different architectures being proposed. This paper presents the state-of-the-art in reconfigurable hardware SAT satisfiers. The analysis and classification of existing systems has been performed according to such criteria as algorithmic issues, reconfiguration modes, the execution model, the programming model, logic capacity, and performance.

A software/reconfigurable hardware SAT solver

This paper introduces a novel approach for solving the Boolean satisfiability (SAT) problem by combining software and configurable hardware. The suggested technique avoids instance-specific hardware compilation and, as a result, allows the total problem solving time to be reduced compared to other approaches that have been proposed. Moreover, the technique permits problems that exceed the resources of the available reconfigurable hardware to be solved. The paper presents the results obtained with some of the DIMACS benchmarks and a comparison of our implementation with other available SAT solvers based on reconfigurable hardware. The hardware part of the satisfier was realized on Virtex XCV812E FPGA, which has a large volume of embedded memory blocks that provide direct support for the proposed approach.

Teaching reconfigurable systems: methods, tools, tutorials, and projects

This paper presents an approach that has been used for teaching disciplines on reconfigurable computing and advanced digital systems, which are intended to cover such topics as architectures and capabilities of field-programmable logic devices; languages for the specification, modeling, and synthesis of digital systems; design methods; computer-aided design tools; reconfiguration techniques; and practical applications. To assist the educational process, the following units have been developed and employed in the pedagogical practice: animated tutorials, miniprojects, hardware templates, and course-oriented library of digital circuits. To stimulate the students activity, an optional project-based evaluation technique has been applied. All the materials that are required for students are available on the university website (WebCT) and can easily be used for studying inside the university, for obtaining additional information during practical classes and for distance learning.

Synthesis and Optimization of FPGA-Based Systems

Part I Design of digital circuits and systems on the basis of FPGA.- Part II Methods for optimization of finite state machines for FPGA-based circuits and systems.

High-performance implementation of regular and easily scalable sorting networks on an FPGA

The paper is dedicated to fast FPGA-based hardware accelerators that implement sorting networks. The primary emphasis is on the uniformity of core components, feasible combinations of parallel, pipelined and sequential operations, and the regularity of the circuits and interconnections. The paper shows theoretically, and based on numerous experiments, that many existing solutions that are commonly considered to be very efficient have worthy competitors that are better for many practical problems. We compared the even-odd merge and bitonic merge sorting networks (which are among the fastest known) with the even-odd transition network, which is often characterized as significantly slower and more resource consuming. We found that the latter is the most regular network that can be implemented very efficiently in FPGA, so we are proposing new, easily scalable hardware solutions and processing techniques based on this. Finally, the paper provides four main contributions and suggests: (1) a regular hardware implementation of resource and time effective architectures based on the even-odd transition network; (2) a pipelined implementation of even-odd transition networks; (3) a pre-processing technique that enables sorting to be further accelerated; (4) combinations of this technique with a merge sort, an address-based sort, a quicksort, and a radix sort.

Implementation in FPGA of Address-Based Data Sorting

The paper describes the hardware implementation and optimization of sorting algorithms that use data items as memory addresses with one-bit flags indicating presence of data. The proposed technique enables such type of address-based sorting to be applied either directly or through tree-walk tables permitting number of bits in sorted data items to be increased by constructing and traversing N-ary trees (N>2) composed of so called no-match and working nodes. The latter are organized in well balanced sub-trees of equal depth. It is allowed more than one data item to be assigned to leaves of working sub-trees and such sets of items are processed by fast acceleration circuits. Experiments and comparisons demonstrate that the proposed technique can be used efficiently in low cost FPGAs.

Design and implementation of parallel hierarchical finite state machines

This paper presents a novel model and method for synthesis of parallel hierarchical finite state machines (PHFSM) that permit to implement algorithms composed of modules in such a way that 1) the modules can be activated from other modules, and 2) more than one module can be activated in parallel. The model combines multiple stack memories interacting with a combinational circuit. The synthesis involves three basic steps: 1) conversion of a given specification to special state transition diagrams; 2) use of the proposed hardware description language templates; 3) synthesis of the circuit from the templates. A number of PHFSMs have been designed, implemented in low-cost commercially available FPGAs, tested, and evaluated. The results of experiments have proven the effectiveness and practicability of the proposed technique for solving real-world problems.

Recursion in reconfigurable computing: A survey of implementation approaches

Reconfigurable systems are widely used nowadays to increase performance of computationally intensive applications. There exist a lot of synthesis tools that automatically generate customized hardware circuits from specifications in both high-level and hardware description languages. However, such tools have a limited applicability because they are unable to handle recursive functions whereas it is known that recursion is a powerful problem-solving method widely used in computer science. Therefore a great deal of research effort is aimed at efficient implementation of recursion in reconfigurable hardware. This paper presents the state of the art in this area. The existing proposals are described, analyzed, and compared according to such criteria as level of parallelism supported, approach to concurrency, ease of use, availability of automated high-level synthesis tools, etc.

Parallel FPGA-Based Implementation of Recursive Sorting Algorithms

The paper describes the hardware implementation and optimization of parallel recursive algorithms that sort data using binary trees. Since recursive calls are not directly supported by hardware description languages, they are implemented using the model of a hierarchical finite state machine (HFSM). Parallel processing is achieved by constructing N binary trees (N>1) and applying concurrent sorting to N trees at the same time with the aid of N communicating HFSMs. The paper presents new results in: 1) parallel sorting algorithms, 2) FPGA-based parallel architectures, and 3) the analysis and comparison of alternative and competitive techniques for implementing parallel recursive algorithms. Experiments demonstrate that the performance of sorting operations is increased compared to previous implementations.

FPGA-Based Implementation of Genetic Algorithm for the Traveling Salesman Problem and Its Industrial Application

In this paper an adaptive distribution system for manufacturing applications is considered and examined. The system receives a set of various components at a source point and supplies these components to destination points. The objective is to minimize the total distance that has to be traveled. At each destination point some control algorithms have to be activated and each segment of motion between destination points has also to be controlled. The paper suggests a model for such a distribution system based on autonomous subalgorithms that can further be linked hierarchically. The links are set up during execution time (during motion) with the aid of the results obtained from solving the respective traveling salesman problem (TSP) that gives a proper tour of minimal length. The paper proposes an FPGA-based solution, which integrates a specialized virtual controller implementing hierarchical control algorithms and a hardware realization of genetic algorithm for the TSP.