António de Brito Ferrari

A software/reconfigurable hardware SAT solver

This paper introduces a novel approach for solving the Boolean satisfiability (SAT) problem by combining software and configurable hardware. The suggested technique avoids instance-specific hardware compilation and, as a result, allows the total problem solving time to be reduced compared to other approaches that have been proposed. Moreover, the technique permits problems that exceed the resources of the available reconfigurable hardware to be solved. The paper presents the results obtained with some of the DIMACS benchmarks and a comparison of our implementation with other available SAT solvers based on reconfigurable hardware. The hardware part of the satisfier was realized on Virtex XCV812E FPGA, which has a large volume of embedded memory blocks that provide direct support for the proposed approach.

FPGA-Based Implementation of Genetic Algorithm for the Traveling Salesman Problem and Its Industrial Application

In this paper an adaptive distribution system for manufacturing applications is considered and examined. The system receives a set of various components at a source point and supplies these components to destination points. The objective is to minimize the total distance that has to be traveled. At each destination point some control algorithms have to be activated and each segment of motion between destination points has also to be controlled. The paper suggests a model for such a distribution system based on autonomous subalgorithms that can further be linked hierarchically. The links are set up during execution time (during motion) with the aid of the results obtained from solving the respective traveling salesman problem (TSP) that gives a proper tour of minimal length. The paper proposes an FPGA-based solution, which integrates a specialized virtual controller implementing hierarchical control algorithms and a hardware realization of genetic algorithm for the TSP.

Design and implementation of reconfigurable processor for problems of combinatorial computations

The paper analyses different techniques that might be employed in order to solve various problems of combinatorial optimization and argues that the best results can be achieved by the use of software, running on a general-purpose computer, together with an FPGA-based reconfigurable co-processor. It suggests architecture of combinatorial co-processor, which is based on hardware templates and consists of reconfigurable functional and control units. Finally the paper demonstrates how to utilize the co-processor for two practical applications formulated over discrete matrices that are satisfiability and covering problems.

A SAT Solver Using Software and Reconfigurable Hardware

Summary form only given. In this paper we propose a novel approach for solving the Boolean satisfiability problem by combining software and reconfigurable hardware. The suggested technique avoids instance-specific hardware compilation and, as a result, achieves a higher performance than pure software approaches. Moreover, it permits problems that exceed the resources of the available reconfigurable hardware to be solved.

The design and implementation of a reconfigurable processor for problems of combinatorial computation

The paper analyses different techniques that might be employed in order to solve various problems of combinatorial optimization and argues that the best results can be achieved by the use of software running on a general-purpose computer together with an FPGA-based reconfigurable co-processor. It suggests an architecture for a combinatorial coprocessor that is based on hardware templates and consists of reconfigurable functional and control units. Finally the paper demonstrates how the co-processor can be applied to two practical applications formulated over discrete matrices, the Boolean satisfiability and covering problems.

A dynamically reconfigurable accelerator for operations over Boolean and ternary vectors

This paper suggests a novel architecture for a reconfigurable accelerator for computations over discrete vectors. The number of executed operations is limited but they can arbitrarily be chosen from a practically unlimited set of feasible operations. The software model and hardware implementations of the accelerator are discussed in detail.

Development system for FPGA-based digital circuits

The paper discusses some new hardware and software tools that can be used for the design of virtual circuits based on dynamically reconfigurable FPGAs. With the aid of these tools we can implement a system that requires some, hardware resources R/sub c/, on available hardware that has resources R/sub h/, where R/sub c/>R/sub h/. The main idea of the approach supported by these tools is the rational combination of FPGA capabilities with some proposed methods for producing a modifiable specification, together with a novel technique for architectural and logic synthesis, which has been incorporated into the new design environment.

Synthesis tools and design environment for dynamically reconfigurable FPGAs

This paper discusses a range of problems in architectural and logic synthesis of digital devices and suggests practical approaches, methods, and tools for the automatic translation of a behavioural specification into a hardware implementation using a dynamically reconfigurable FPGA of the XC6200 family. The work described in this paper covers two basic areas. Firstly, new FPGA-oriented methods for behavioural synthesis of virtual digital circuits within predefined scopes are presented Secondly, an integrated design environment for logic synthesis (IDELS) is described which has been implemented as an extension of commercially available tools. IDELS permits synthesis in accordance with the developed design flow and offers very powerful run-time debugging facilities, including support for dynamic reconfiguration.

An Object-Oriented framework for CAN protocol modeling and simulation

Abstract This paper presents an object-oriented software framework created with the aim of modeling and simulating distributed applications based on the CAN protocol. The created infrastructure consists of a modular simulator that allows describing all the system components, namely the interconnection bus and the distributed nodes. The object-oriented programming paradigm is used to simplify the modular implementation of the several protocol layers. The simulator was written in C++ and can be used as an executable specification to assist in the hardware implementation of a CAN controller.

Software parallel implementation of a DS-CDMA Multiuser Detector

In this article the complexity and runtime performance of two Multiuser Detectors for Direct Sequence-Code Division Multiple Access were evaluated in two hardware platforms in order of a possible deployment in base stations. The detectors are based on the Frequency Shift Canceller concatenated with a Parallel Interference Canceller. This detector is very scalable which shadows the complexity penalty of a serial implementation in which other detectors have advantage. Implementations for the Time Division-Code Division Multiple Access deployed in China, in two software platforms one in OpenMP and other in CUDA were done. It is demonstrated that a realtime implementation is possible with a General Propose Graphics Processor Unit. This is part of a broader project aiming to take advantage of present parallel hardware to bring improved Multiuser technology to the present and future Base Stations, mainly in Universal Mobile Telecommunications System-Time Division Duplex.