Iraklis Anagnostopoulos

Distributed run-time resource management for malleable applications on many-core platforms

Todays prevalent solutions for modern embedded systems and general computing employ many processing units connected by an on-chip network leaving behind complex superscalar architectures In this paper, we couple the concept of distributed computing with parallel applications and present a workload-aware distributed run-time framework for malleable applications on many-core platforms. The presented framework is responsible for serving in a distributed way and at run-time, the needs of malleable applications, maximizing resource utilization avoiding dominating effects and taking into account the type of processors supporting platform heterogeneity, while having a small overhead in overall inter-core communication. Our framework has been implemented as part of a C simulator and additionally as a runtime service on the Single-Chip Cloud Computer (SCC), an experimental processor created by Intel Labs, and we compared it against a state-of-art run-time resource manager. Experimental results showed that our framework has on average 70% less messages, 64% smaller message size and 20% application speed-up gain.

A divide and conquer based distributed run-time mapping methodology for many-core platforms

Real-time applications are raising the challenge of unpredictability. This is an extremely difficult problem in the context of modern, dynamic, multiprocessor platforms which, while providing potentially high performance, make the task of timing prediction extremely difficult. In this paper, we present a flexible distributed run-time application mapping framework for both homogeneous and heterogeneous multi-core platforms that adapts to applications needs and applications execution restrictions. The novel idea of this article is the application of autonomic management paradigms in a decentralized manner inspired by Divide-and-Conquer (D&C) method. We have tested our approach in a Leon-based Network-on-Chip platform using both synthetic and real application workload. Experimental results showed that our mapping framework produces on average 21% and 10% better on-chip communication cost for homogeneous and heterogeneous platform respectively.

Custom multi-threaded Dynamic Memory Management for Multiprocessor System-on-Chip platforms

We address the problem of custom Dynamic Memory Management (DMM) in Multi-Processor System-on-Chip (MPSoC) architectures. Customization is enabled through the definition of a design space that captures in a global, modular and parameterized manner the primitive building blocks of multi-threaded DMM. A systematic exploration methodology is proposed to efficiently traverse the design space. Customized Pareto DMM configurations are automatically generated through the development of software tools implementing the proposed methodology. Experimental evaluation based on a real-life multithreaded dynamic network application show that the proposed methodology delivers higher quality (application-specific) solutions in comparison with state-of-the-art dynamic memory managers together with 62% exploration runtime reductions.

Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations

Multiprocessor system-on-chip (MPSoCs) have attracted significant attention since they are recognized as a scalable paradigm to interconnect and organize a high number of cores. Current multicore embedded systems exhibit increased levels of dynamic behavior, leading to unexpected memory footprint variations unknown at design time. Dynamic memory management (DMM) is a promising solution for such types of dynamic systems. Although some efficient dynamic memory managers have been proposed for conventional bus-based MPSoC platforms, there are no DMM solutions regarding the constraints and the opportunities delivered by the physical distribution of multiple memory nodes of the platform. In this work, we address the problem of providing customized microcoded DMM on MPSoC platforms with distributed memory organization. Customization is enabled at application- and platform-level. Results show that customized microcoded DMM can serve approximately 7× more allocation requests compared to pure distributed memory platforms and perform 25% faster than the corresponding high-level implementation in C language.

Node resource management for DSP applications on 3D Network-on-Chip architecture

Emerging DSP applications have different latency, energy consumption and Quality of Service (QoS) requirements. An implementation of such applications requires a large number of intellectual property (IP) cores, communicating with each other, meeting the energy and latency constraints. Network-on-Chip (NoC) architectures is able to accommodate a large number of IP cores in the same chip implementing a set of complex applications. This leads to different usage of the available buffer space in the routers of the NoC system. In this work we propose power and the systematic design of novel NOC-based architectures, which realize DSP applications. Additionally, we present an integrated node resource management technique that combines priority assignment and buffer sizing so that the NoC system to best serve requirements of the considered Finally, to best of our knowledge, the implementation of DSP applications in 3D NOC architectures took place for first time. DSP applications. The proposed approach has been evaluated both on 2D and 3D mesh topologies by employing an NoC simulator and four real DSP/multimedia applications gaining an average of 34% on energy×delay product for each application. Finally, to best of our knowledge, the implementation of DSP applications in 3D NOC architectures took place for first time.

A High-Level Mapping Algorithm Targeting 3D NoC Architectures with Multiple Vdd

The communication problem in modern ICs becomes a challenge issue. This paper introduces a high-level mapping algorithm targeting to low-power 3D NoC devices. By appropriately assigning applications functionalities to layers with different supply voltages we achieve reasonable energy savings and temperature reduction. Additionally, our methodology supports real-time adaption on different traffic scenarios. Experimental results show that energy savings up to 19% are feasible, without any area and delay overhead, as compared to architectures powered by only one supply voltage.

SPARTAN project: Efficient implementation of computer vision algorithms onto reconfigurable platform targeting to space applications

Vision-based robotic applications exhibit increased computational complexity. This problem becomes even more important regarding mission critical application domains. The SPARTAN project focuses in the tight and optimal implementation of computer vision algorithms targeting to rover navigation for space applications. For evaluation purposes, these algorithms will be implemented with a co-design methodology onto a Virtex-6 FPGA device.

Application-specific temperature reduction systematic methodology for 2d and 3d networks-on-chip

Network-on-Chip (NoC), a new SoC paradigm, has been proposed as a solution to mitigate complex on-chip interconnection problems. NoC architectures are able to accommodate a large number of IP cores in the same chip implementing a set of complex applications. Power consumption is a critical issue in interconnection network in NoC design, driven by power-related design constraints, such as thermal and power delivery design. In this work, we introduce a systematic methodology for NoC temperature reduction consisting of novel techniques: i) application independent power-aware routing algorithms; and ii) application-specific platform optimizations, such as buffer sizing. The methodology achieves significant peak temperature reduction. The effectiveness of the proposed approach is evaluated both on 2D and 3D mesh topologies employing real DSP applications. A temperature reduction of 13°C and 22°C for 2D and 3D NoCs, respectively, on average, is achieved without any performance penalty.

Power-aware dynamic memory management on many-core platforms utilizing DVFS

Today multicore platforms are already prevalent solutions for modern embedded systems. In the future, embedded platforms will have an even more increased processor core count, composing many-core platforms. In addition, applications are becoming more complex and dynamic and try to efficiently utilize the amount of available resources on the embedded platforms. Efficient memory utilization is a key challenge for application developers, especially since memory is a scarce resource and often becomes the systems bottleneck. To cope with this dynamism and achieve better memory footprint utilization (low memory fragmentation) application developers resort to the usage of dynamic memory (heap) management techniques, by allocating and deallocating data at runtime. Moreover, overall power consumption is another key challenge that needs to be taken into consideration. Towards this, designers employ the usage of Dynamic Voltage and Frequency Scaling (DVFS) mechanisms, adapting to the applications computational demands at runtime. In this article, we propose the combination of dynamic memory management techniques with DVFS ones. This is performed by integrating, within the memory manager, runtime monitoring mechanisms that steer the DVFS mechanisms to adjust clock frequency and voltage supply based on heap performance. The proposed approach has been evaluated on a distributed shared-memory many-core platform composed of multiple LEON3 processors interconnected by a Network-on-Chip infrastructure, supporting DVFS. Experimental results show that by using the proposed method for monitoring and applying DVFS mechanisms the power consumption concerning dynamic memory management was reduced by approximately 37%. In addition we present the trade-offs the proposed approach. Last, by combining the developed method with heap fragmentation-aware dynamic memory managers, we achieve low heap fragmentation values combined with low power consumption.

Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures

Network-on-Chip (NoC), a new System-on-Chip paradigm, has been proposed as a solution to mitigate complex on-chip interconnection problems. NoC architectures are able to accommodate a large number of IP cores in the same chip implementing a set of complex applications. Especially, custom NoC topologies are able to further increase application’sperformance due to their adaptiveness. In this paper, we present a systematic methodology for generating an energy efficient application-specific NoC architecture. The methodology framework consists of the following steps: 1) greedy application partitioning, 2) automatic topology generation and extensive exploration, and 3) an energy-aware router optimization so as to find the best architecture that meets applications requirements. Validation of the proposed framework was performed using four DSP/multimedia applications showing that energy-aware irregular NoCs can achieve on average 53% energy reduction, without violating applications timing constrains.