Isa Servan Uzun

A segmentation concept for positron emission tomography imaging using multiresolution analysis

Positron emission tomography (PET) imaging is an emerging medical imaging modality. Due to its high sensitivity and ability to model function, it is effective in identifying active regions that may be associated with various types of tumours. Increasing numbers of patient scans have led to an urgent need for efficient data archival and the development of new image analysis techniques to aid clinicians in the diagnosis of disease. Additionally, to handle the large volumes of data generated using complex processing algorithms, it is becoming evident that co-processing solutions are essential. In this paper, an automated system for the segmentation of oncological PET data is developed. Initially, the Bayesian information criterion (BIC) is utilised for optimal segmentation level selection. Expectation maximisation (EM) based mixture modelling is then performed, using a k-means clustering procedure which varies voxel order for initialisation. A multiscale Markov model is then used to refine this segmentation by modelling spatial correlations between neighbouring image voxels. A field programmable gate array (FPGA) based co-processing solution is also proposed to offload the most complex computations onto hardware, in order to achieve high performance.

Design and FPGA implementation of finite Ridgelet transform [image processing applications]

The Ridgelet transform was recently introduced to overcome the weakness of wavelets in higher dimensions. In this paper, we present the design and FPGA implementation of the finite Ridgelet transform (FRIT) for image processing applications. The proposed architecture uses the finite Radon transform (FRAT) and 1D discrete biorthogonal wavelet transform (DBWT) as building blocks. A detailed evaluation of the FPGA implementation for the proposed architectures targeting the Xilinx Virtex-II device family has been reported, based on maximum system frequency, chip area and image size. The implementation results show that the core speed for the proposed FRIT architecture is around 100 MHz and it occupies 491 slices for an input image size of 7/spl times/7.

Real-time 2-D wavelet transform implementation for HDTV compression

Recent advances in image analysis have shown that the application of 2-D discrete biorthogonal wavelet transform (DBWT) to digital image compression overcomes some of the barriers imposed by block-based transform coding algorithms while offering significant advantages in terms of coding gain, quality, natural compatibility with video formats requiring lower-resolution and graceful performance degradation when compressing at low bit rates. This paper reports on the design and field programmable gate array (FPGA) implementation of a non-separable 2-D DBWT architecture which is the heart of the proposed high-definition television (HDTV) compression system. The architecture adopts periodic symmetric extension at the image boundaries, therefore it conforms the JPEG-2000 standard. It computes the DBWT decomposition of an NxN image in approximately 2N^2/3 clock cycles (ccs). Hardware implementation results based on a Xilinx Virtex-2000E FPGA chip showed that the processing of 2-D DBWT can be performed at 105MHz providing a complete solution for the real-time computation of 2-D DBWT for HDTV compression.

Towards a general framework for an FPGA-based FFT coprocessor

There have been a large number of fast Fourier transform (FFT) algorithms which have been developed over the years. Among these algorithms, the most promising are the Radix-2, Radix-4, Split-Radix and fast Hartley transform (FHT). In this paper we present an investigation into the design and implementation of the above mentioned FFT algorithms using Handel-C - a recently developed C-like programming language for compilation of high-level programs directly into FPGA hardware. The algorithms have been implemented and verified on the Celocixa RC1000 FPGA development board. A detailed evaluation has also been reported based on maximum system frequency, chip area and computation time.

Design and FPGA implementation of nonseparable 2-D biorthogonal wavelet transforms for image/video coding

This paper reports on the design and hardware implementation of an efficient architecture for the nonseparable 2-D discrete biorthogonal wavelet transforms (DBWT). The architecture adopts periodic symmetric extension at the image boundaries, therefore it conforms the JPEG-2000 standard. It computes the DBWT decomposition of an NxN image in approximately 2N/sup 2//3 clock cycles (ccs). Hardware implementation results based on a Xilinx Virtex-2000E FPGA chip showed that the processing of 2-D DBWT can be performed at 105 MHz providing a complete solution for the real-time computation of 2-D DBWT with image boundary handling.

An FPGA implementation of 3D affine transformations

3D graphics performance is increasing faster than any other computing application. Almost all PC systems now include 3D graphics accelerators for games, Computer Aided Design (CAD) or visualization applications. This paper investigates the suitability of Field Programmable Gate Array (FPGA) devices as a low cost solution for implementing 3D affine trans formations. A proposed solution based on processing large matrix multiplication has been implemented, for large 3D models, on the RC1000-PP Celoxica board based development platform using Handel-C, a C-like language supporting parallelism, flexible data size and compilation of high-level programs directly into FPGA hardware.

A reconfigurable coprocessor for high-resolution image filtering in real time

Applications based on Fast Fourier Transform (FFT) such as signal and image processing require high computational power, plus the ability to experiment with algorithms. To try to meet the dual requirements of high performance and ease of development, in this work we present a High Level framework for the implementation of FFTs for real-time image processing applications. The frequency-domain (convolution-based) image filtering problem is targeted by developing an FPGA-based parametrisable environment based on the proposed parallel 2-D FFT architecture for real-time operation. Results show that the parallel implementation of 2-D FFT achieves virtually linear speed-up and real-time performance for large matrix sizes.

An efficient architecture for 1-D discrete biorthogonal wavelet transform

Biorthogonal wavelets offer improved coding gain and an efficient treatment of signal boundaries. In this paper, we propose a high-speed/high-throughput architecture for 1-D Discrete Biorthogonal Wavelet Transform (DBWT). This architecture performs 1-D DBWT decomposition of an N/sub 0/-sample input signal with K decomposition levels in N/sub 0//2 clock cycles. Therefore, it is at least twice as fast as other known DBWT architectures. The architecture offers efficient hardware utilisation for VLSI implementation by combining the linear phase property of biorthogonal filters with decimation.

A FPGA-based parametrizable system for high-resolution frequency-domain image filtering

Signal and image processing applications require high computational power with the ability to experiment different algorithms involving matrix transforms. Reconfigurable hardware devices in the form of Field Programmable Gate Arrays (FPGAs) have been proposed to obtain high performance at an economical price. However, the users must program FPGAs at a very low level and must have a detailed knowledge of the architecture of the device being used. In trying to reconcile the dual requirements of high performance and the ease of development, this paper reports the design and realization of the Fast Fourier Transforms (FFTs) using a FPGA-based environment, which enables system designer to meet different system requirements (i.e., chip area, speed, memory, etc.) for a range of signal processing and imaging applications. The use of the proposed environment has been proven by the developing a high-level FPGA-based parametrizable image processing system for frequency-domain filtering application. The system achieves real-time image filtering performance exceeding those of currently available solutions by an order of magnitude in frame rate and input image size.

A high-speed/low-power architecture for 1D discrete biorthogonal wavelet transform

Biorthogonal wavelets offer improved coding gain and an efficient treatment of boundaries in signal coding applications. In this paper, we propose a scalable pipelined architecture that performs 1D discrete biorthogonal wavelet transform (DBWT) with K decomposition levels in N/sub 0//2 clock cycles. Therefore, it is at least twice as fast as other known DBWT architectures. The performance of the architecture has been verified and evaluated by implementations on Xilinx Virtex-2000E FPGA chip. Very high data-throughput rates up to 320 MegaSamples/sec, with efficient hardware utilisation have been achieved.