Faycal Bensaali

OCR-based neural network for ANPR

Optical Character Recognition (OCR) is the last stage in an Automatic Number Plate Recognition System (ANPRs). In this stage the number plate characters on the number plate image are converted into encoded texts. In this paper, an Artificial Neural Network (ANN) based OCR algorithm for ANPR application is presented. A database of 3700 UK binary character images have been used for testing the performance of the proposed algorithm. Results achieved have shown that the proposed algorithm can meet the real-time requirement of an ANPR system and can averagely process a character image in 8.4ms with 97.3% successful recognition rate.

Real-time optical character recognition on field programmable gate array for automatic number plate recognition system

The last main stage in an automatic number plate recognition system (ANPRs) is optical character recognition (OCR), where the number plate characters on the number plate image are converted into encoded texts. In this study, an artificial neural network-based OCR algorithm for ANPR application and its efficient architecture are presented. The proposed architecture has been successfully implemented and tested using the Mentor Graphics RC240 field programmable gate arrays (FPGA) development board equipped with a 4M Gates Xilinx Virtex-4 LX40. A database of 3570 UK binary character images have been used for testing the performance of the proposed architecture. Results achieved have shown that the proposed architecture can meet the real-time requirement of an ANPR system and can process a character image in 0.7 ms with 97.3% successful character recognition rate and consumes only 23% of the available area in the used FPGA.

Floating-Point Matrix Product on FPGA

The nature of some scientific computing applications involves performing complex tasks repeatedly on floating-point data, often under real-time requirements. Therefore, high performance systems are required by the developers for fast computations. Many researchers have begun to recognize the potential of reconfigurable hardware such as field-programable gate arrays in implementing floating-point arithmetic. In this paper a floating-point adder and multiplier are presented. The proposed cores are used as basic components for the implementation of a parallel floating-point matrix multiplier designed for 3D afflne transformations. The cores have been implemented on recent FPGA devices. The performance in terms of area/speed of the proposed architectures has been assessed and has shown that they require less area and can be run with a higher frequency when compared with existing systems.

Comparison of real-time DSP-based edge detection techniques for license plate detection

In this paper, edge detection techniques and their performance are compared when applied in license plate detection using an embedded digital signal processor. License plate detection remains to be the crucial part of a vehicles license plate recognition process. The edge detection algorithms compared in this work are those reported capable of delivering real-time performance. These are Canny-Deriche-FGL, Haar and Daubechies-4 wavelet transform and the classic Sobel. These particular algorithms are chosen and compared due to their good performance on digital signal processors. The comparison is drawn in terms of speed and detection success of a license plate. The results show Haar wavelet-based edge detector performs better on a DSP with LP detection speed of 7.32 ms and 98.6% success using 45,032 UK images containing license plates at 768×288 resolutions.

Improved number plate character segmentation algorithm and its efficient FPGA implementation

Character segmentation is an important stage in Automatic Number Plate Recognition systems as good character separation leads to a high recognition rate. This paper presents an improved character segmentation algorithm based on pixel projection and morphological operations. An efficient architecture based on the proposed algorithm is also presented. The architecture has been successfully implemented and verified using the Mentor Graphics RC240 FPGA (Field Programmable Gate Arrays) development board equipped with a 4M-Gate Xilinx Virtex-4 LX40. A database of 1,000 UK binary NPs with varying resolution has been used for testing the performance of the proposed architecture. Results achieved have shown that the proposed architecture can process a number plate image in 0.2–1.4xa0ms with 97.7xa0% successful segmentation rate and consumes only 11xa0% of the available area in the used FPGA.

Real-time license plate localisation on FPGA

Automatic Number Plate Recognition (ANPR) systems have become an important tool to track stolen car, access control and monitor the traffic. The fundamental requirements of an ANPR system are image capture using an ANPR camera, and processing of the captured image. The image processing part, which is a computationally intensive task, includes two stages i.e. plate localisation and character recognition. This paper presents an improved license plate localisation (LPL) algorithm based on modified Sobel vertical edge detection operator and two morphological operations suitable for FPGA implementation. The algorithm has been successfully implemented on a Xilinx Virtex-4 FPGA and tested using a database of 1000 images that contains UK number plates. It consumes 28% of the available on-chip resources, runs with a maximum frequency of 114.20 MHz, has a detection rate of 99.1% and capable of processing one image (640×480) in 3.8ms.

Automatic number plate recognition system on an ARM-DSP and FPGA heterogeneous SoC platforms

The ARM-DSP based ANPR system described is designed for commercial applications where the need for low power, low prices and real time systems is vital. A single FPGA can also be added as a plug-in to the ARM-DSP based hardware SoC, depending on the extra resources needed for the application. The overall results have shown that it is possible to use cheaper off-the-shelf ARM-DSPs and FPGAs multicore processors for standalone ANPR systems through device and algorithm optimisation to achieve real-time performance at higher recognition rate using efficient algorithms.

Improved number plate localisation algorithm and its efficient field programmable gate arrays implementation

Number plate localisation is a very important stage in an automatic number plate recognition (ANPR) system and is computationally intensive. This study presents a low complexity with high-detection rate number plate localisation algorithm based on morphological operations together with an efficient multiplier-less architecture based on that algorithm. The proposed architecture has been successfully implemented and tested using a Mentor Graphics RC240 FPGA (field programmable gate arrays) development board equipped with a 4M-gate Xilinx Virtex-4 LX40. Two database sets sourced from the UK and Greece and including 1000 and 307 images, respectively, both with a resolution of 640 × 480, have been used for testing. Results achieved have shown that the proposed system can process an image in 4.7 ms, while achieving a 97.8% detection rate and consuming only 33% of the available area of the FPGA.

Power Modeling and Efficient FPGA Implementation of Color Space Conversion

In this paper we present a design for an efficient FPGA implementation of a color space converter in video compression. The proposed architecture is based on distributed arithmetic principles has been implemented on the Xilinx Virtex-2000E FPGA using a hybrid design approach combining Handel-C and VHDL. Maximum optimization of performance metrics including frequency and power has been achieved by careful manual floor planning of the design, with particular attention paid to the critical paths and pin assignment. Additionally, a novel functional level power analysis and modeling using non-linear regression analysis has been developed using power and energy data obtained for different combinations of system parameters.

Field programmable gate arrays-based number plate binarization and adjustment for automatic number plate recognition systems

Abstract. Number plate (NP) binarization and adjustment are important preprocessing stages in automatic number plate recognition (ANPR) systems and are used to link the number plate localization (NPL) and character segmentation stages. Successfully linking these two stages will improve the performance of the entire ANPR system. We present two optimized low-complexity NP binarization and adjustment algorithms. Efficient area/speed architectures based on the proposed algorithms are also presented and have been successfully implemented and tested using the Mentor Graphics RC240 FPGA development board, which together require only 9% of the available on-chip resources of a Virtex-4 FPGA, run with a maximum frequency of 95.8 MHz and are capable of processing one image in 0.07 to 0.17 ms.