Isabel Y. Yang

Back-gated CMOS on SOIAS for dynamic threshold voltage control

The simultaneous reduction of power supply and threshold voltages for low-power design without suffering performance losses will eventually reach the limit of diminishing returns as static leakage power dissipation becomes a significant portion of the total power consumption. This is especially acute in systems that are idling most of the time. In order to meet the opposing requirements of high performance at reduced power supply voltage and low-static leakage power during idle periods, a dynamic threshold voltage control scheme is proposed. A novel Silicon-On-Insulator (SOI)-based technology called Silicon-On-Insulator-with-Active-Substrate (SOIAS) was developed whereby a back-gate is used to control the threshold voltage of the front-gate; this concept was demonstrated on a selectively scaled CMOS process implementing discrete devices and ring oscillators. For a 250 mV switch in threshold voltage, a reduction of 3-4 decades in subthreshold leakage current was measured.

Design considerations and tools for low-voltage digital system design

Aggressive voltage scaling to 1 V and below through technology, circuit, and architecture optimization has been proven to be the key to ultra low-power design. The key technology trends for low-voltage operation are presented including low-threshold devices, multiple-threshold devices, and SOI and bulk-CMOS based variable threshold devices. The requirements on CAD tools that allow designers to choose and optimize various technology, circuit, and system parameters are also discussed.

Back gated CMOS on SOIAS for dynamic threshold voltage control

Simultaneous reduction of supply and threshold voltages for low power design without suffering performance losses will eventually reach the limit of diminishing returns as static power dissipation becomes a significant portion of the total power equation. In order to meet the opposing requirements of high performance and low power, a dynamic threshold voltage control scheme is needed. A novel SOI technology was developed whereby a back-gate was used to control the threshold voltage of the front-gate; this concept was demonstrated on a selectively scaled CMOS process.

X-ray nanolithography: Extension to the limits of the lithographic process

The unique aspects of x-ray lithography that make it attractive for the sub-100nm domain include: a highly localized, sharply peaked point-spread function, leading to minimal proximity effects; absence of spurious scattering; an intrinsic resolution below 30 nm; compatibility with all pattern geometries; and parallel exposure (i.e., compatibility with volume production). The major problem areas are: the mask-sample gap (less than 5 @mm for linewidths below 70 nm), and absorber stress, which must be near zero to avoid mask distortion. Nanometer-level pattern placement and alignment are considered achievable by means of spatial-phase-locked e-beam lithography and interferometric-broad-band imaging, respectively. The efficacy of x-ray nanolithography has been demonstrated via the fabrication of a variety of sub-100 nm-featured quantum-effect devices, Si MOSFETs, and grating-based optoelectronic devices. In the event that the small gaps required of proximity x-ray nanolithography prove unacceptable in manufacturing, x-ray projection using arrays of zone plates appears to be the only approach that can employ the optimal wavelengths (i.e., ~1 nm or 4.5 nm) and achieve deep sub-100 nm resolution. A scheme is proposed that employs an array of zone plates in a pattern generator mode.

Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM

The gate tunneling current for gate oxide thickness around 2.0 nm or below has been known to increase device leakage and power dissipation, and deteriorate device performance and circuit stability in bulk CMOS. Recently, direct tunneling current models for bulk CMOS circuit simulations have been developed (Choi et al., 1999; Lee and Hu, 2000). The gate-to-substrate tunneling current resulting from the electron tunneling from the valence band (EVB) is significantly less than the tunneling current from the channel into the gate, and its effect can usually be neglected in bulk CMOS devices and circuits. For floating-body partially-depleted (PD) SOI devices, however, the gate-to-body tunneling current charges/discharges the floating-body, thus changing the body voltage and V/sub T/ and affecting circuit operation (Fung et al., 2000). In this paper, we present a detailed study of the effect of gate tunneling current on a high performance 34 Kb L1 directory SRAM in a 1.5 V, 0.18 /spl mu/m PD/SOI technology with L/sub eff/=0.08 /spl mu/m and t/sub ox/=2.3 /spl mu/m. This SRAM was originally designed in a 1.5 V, 0.18 /spl mu/m bulk CMOS technology and has achieved 2.0 GHz cycle time and 430 ps access time (Joshi et al., 2000). It utilizes pseudo-static circuits for robust timing and to facilitate migration to PD/SOI technology.

Impact of the gate-to-body tunneling current on SOI history effect

The gate dielectric thickness has been aggressively scaled in recent technology generations. The thin gate dielectric is essential to maintain and improve the performance at reduced supply voltages and to control the short-channel effect. For very thin dielectrics, the gate tunneling current becomes noticeable. A component of this tunneling current is comprised of the body majority carriers tunneling from the body to the gate or vice versa. As a result, in SOI MOSFETs, the floating body potential and the history effect are affected by this current in addition to the diode leakage and impact ionization currents. In this paper, we study the impact of gate-to-body tunneling on SOI history effect for the first time.

SOIAS: dynamically variable threshold SOI with active substrate

This paper describes a low voltage, silicon on insulator, active substrate (SOIAS) technology which addresses the problems of increased leakage currents in high performance, low voltage circuits. The threshold voltage is dynamically variable through the application of a voltage to an insulated back gate for high performance and low leakage.

Fundamentals of epitaxial silicon film thickness measurements using emission and reflection Fourier transform infrared spectroscopy

A theoretical analysis of the principles and results of film thickness measurements using a reflection and an emission Fourier transform infrared spectrometer (FT‐IR) is presented. Epitaxial film thickness measurements by emission FT‐IR (E/FT‐IR) have been recently demonstrated and the study reported here was conducted to understand further the underlying physical principles. The theoretical basis for spatial Fourier transformation using the Michelson interferometer is introduced. Moreover, a transfer function for a linear system model of the Michelson interferometer is derived. The transfer function and the model are subsequently used to calculate interferograms, which agree well with our experimentally measured interferograms. The difference in the interferograms obtained by IR reflection and IR emission is explained theoretically. The limitation of the FT‐IR techniques is discussed. Furthermore, a comparison of the reflection FT‐IR and emission FT‐IR for epitaxial film thickness measurement will be giv...

High performance self‐aligned sub‐100 nm metal–oxide‐semiconductor field‐effect transistors using x‐ray lithography

Recent studies have shown that high performance 0.1 μm complementary metal–oxide semiconductor (CMOS) can be achieved with proper channel and source/drain engineering. Specifically, retrograde channel doping and shallow source/drain junctions with counterdoping implant (halo) allow the threshold voltage to be kept low while maintaining acceptable short‐channel behavior. These studies have certainly demonstrated the feasibility of CMOS technology scaled down to 0.1 μm from a device design point‐of‐view. However, the main challenge to the lithography technology is to fabricate 0.1 μm metal‐oxide‐semiconductor field‐effect transistor (MOSFET) devices with high yield and high throughput, as required in manufacturing. X‐ray lithography is a technology that can potentially meet this challenge. This work shows the results of integrating a low cost x‐ray technology with standard IC processing to fabricate high performance 100 nm and even sub‐100 nm MOSFETs.

Combining and matching optical, electron‐beam, and x‐ray lithographies in the fabrication of Si complementary metal–oxide–semiconductor circuits with 0.1 and sub‐0.1 μm features

In the fabrication of large‐area Si complementary metal–oxide–semiconductor circuits with 100 and sub‐100 nm features, it is inefficient to use direct‐write electron‐beam (e‐beam) lithography for all of the layers, in part because of the exceedingly long writing times. Instead, a strategy of ‘‘mix and match’’ is preferred, in which coarse features on all layers are defined by optical projection and only the fine features are written by e‐beam lithography. We describe a strategy that combines optical, e‐beam, and x‐ray lithographies, and solves the problem of scale matching and distortion in such a mix‐and‐match scheme. Layers that include only coarse features are exposed directly on Si wafers using a G‐line stepper. This same stepper is also used to expose, on a chrome‐coated quartz wafer, arrays of e‐beam field alignment marks along with any coarse features required in this ‘‘critical layer.’’ This pattern is then transferred by deep ultraviolet proximity printing onto an x‐ray mask and plated up in gold. The e‐beam writes the fine features using the e‐beam field‐alignment marks as reference. Because the arrangement of the e‐beam field‐alignment marks reflects the distortion and scale of the optical stepper, overlay in the final circuit on the wafer is ensured. Furthermore, considerable e‐beam writing time is saved. The final pattern is transferred onto the device wafers using x‐ray lithography.