Rafael Reif

Interconnect limits on gigascale integration (GSI) in the 21st century

Twenty-first century opportunities for GSI will be governed in part by a hierarchy of physical limits on interconnects whose levels are codified as fundamental, material, device, circuit, and system. Fundamental limits are derived from the basic axioms of electromagnetic, communication, and thermodynamic theories, which immutably restrict interconnect performance, energy dissipation, and noise reduction. At the material level, the conductor resistivity increases substantially in sub-50-nm technology due to scattering mechanisms that are controlled by quantum mechanical phenomena and structural/morphological effects. At the device and circuit level, interconnect scaling significantly increases interconnect crosstalk and latency. Reverse scaling of global interconnects causes inductance to influence on-chip interconnect transients such that even with ideal return paths, mutual inductance increases crosstalk by up to 60% over that predicted by conventional RC models. At the system level, the number of metal levels explodes for highly connected 2-D logic megacells that double in size every two years such that by 2014 the number is significantly larger than ITRS projections. This result emphasizes that changes in design, technology, and architecture are needed to cope with the onslaught of wiring demands. One potential solution is 3-D integration of transistors, which is expected to significantly improve interconnect performance. Increasing the number of active layers, including the use of separate layers for repeaters, and optimizing the wiring network, yields an improvement in interconnect performance of up to 145% at the 50-nm node.

Recrystallization of amorphized polycrystalline silicon films on SiO2: Temperature dependence of the crystallization parameters

This paper presents a theoretical and experimental study of the recrystallization behavior of polycrystalline silicon films amorphized by self‐implantation. The crystallization behavior was found to be similar to the crystallization behavior of films deposited in the amorphous state, as reported in the literature; however, a transient time was observed, during which negligible crystallization occurs. The films were prepared by low‐pressure chemical vapor deposition onto thermally oxidized silicon wafers and amorphized by implantation of silicon ions. The transient time, nucleation rate, and characteristic crystallization time were determined from the crystalline fraction and density of grains in partially recrystallized samples for anneal temperatures from 580 to 640 °C. The growth velocity was calculated from the nucleation rate and crystallization time and is lower than values in the literature for films deposited in the amorphous state. The final grain size, as calculated from the crystallization param...

System-level performance evaluation of three-dimensional integrated circuits

In this paper, the wire (interconnect)-length distribution of three-dimensional (3-D) integrated circuits (ICs) is derived using Rents rule and following the methodology used to estimate two-dimensional (2-D) (wire-length distribution). Two limiting cases of connectivity between logic gates on different device layers are examined by comparing the wire-length distribution and average and total wire-length. System performance metrics such as clock frequency, chip area, etc., are estimated using wire-length distribution, interconnect delay criteria, and simple models representing the cost or complexity for manufacturing 3-D ICs. The technology requirement for interconnects in 3-D integration is also discussed.

Polycrystalline silicon thin films processed with silicon ion implantation and subsequent solid-phase crystallization: Theory, experiments, and thin-film transistor applications

A review is presented of the self‐implantation method which has been developed to achieve high‐quality polycrystalline silicon thin films on insulators with enhanced grain sizes and its applications to thin‐film transistors (TFTs). In this method, silicon ions are implanted into an as‐deposited polycrystalline silicon thin film to amorphize most of the film structure. Depending on ion implantation conditions, some seeds with 〈110〉 orientation remain in the film structure due to channeling. The film is then thermally annealed at relatively low temperatures, typically in the range of 550–700 °C. With optimized process conditions, average grain sizes of 1 μm or greater can be obtained. First, an overview is given of the thin‐film transistor technology which has been the greatest motivation for the research and development of the self‐implantation method. Then the mechanism of selective amorphization by the silicon self‐implantation and the crystallization by thermal annealing is discussed. An analytical mode...

Wiring requirement and three-dimensional integration technology for field programmable gate arrays

In this paper, analytical models for predicting interconnect requirements in field-programmable gate arrays (FPGAs) are presented, and opportunities for three-dimensional (3-D) implementation of FPGAs are examined. The analytical models for two-dimensional FPGAs are calibrated by routing and placement experiments with benchmark circuits and extended to 3-D FPGAs. Based on system-level modeling, we find that in FPGAs with more than 20 K four-input look-up tables, the reduction in channel width, interconnect delay and power dissipation can be over 50% by 3-D implementation.

Silicon epitaxy at 650–800 °C using low‐pressure chemical vapor deposition both with and without plasma enhancement

A system and a procedure using chemical vapor deposition of silane at very low pressures (<10−2 Torr) have been developed for depositing uniform, specular silicon epitaxial films both with and without plasma enhancement at temperatures as low as 650 °C. In situ cleaning of the substrate surface that overlaps into the deposition is the most critical aspect of the procedure. Undoped films deposited on substrates heavily doped with antimony or boron have abrupt doping profiles. Preliminary measurements indicate that the hole mobility of epitaxial films obtained with this process is 90% of that in bulk silicon. Films oxidized and decorated with a Secco etch show twice as many defects as a similarly treated substrate. Nonplasma growth kinetics are sensitive to surface conditions such as crystallographic orientation, and surface diffusion of adsorbed species appears to be the rate‐limiting step for depositing epitaxial films above 700 °C. Around 650 °C, the growth mechanism appears to change, possibly due to th...

Technology, performance, and computer-aided design of three-dimensional integrated circuits

We present an overview of a new monolithic fabrication technology known as three-dimensional integration. 3D integration refers to any process by which multiple conventional device layers may be stacked and electrically interconnected. By combining state-of-the-art single-wafer integration with a high-density inter-wafer interconnect, our 3D integration process is capable of providing improved circuit performance in terms of metrics such as wire length, area, timing, and energy consumption. In this paper, we will discuss the overall 3D integration process flow, as well as specific technological challenges and the issues they present to circuit designers. We will also describe how these issues may be tackled during the placement, routing, and layout stages of physical design. Finally, we will present some performance results that may be obtained by integrating circuits in three dimensions.

Fabrication technologies for three-dimensional integrated circuits

The MIT approach to 3D VLSI integration is based on low-temperature Cu-Cu wafer bonding. Device wafers are bonded in a face-to-back manner, with short vertical vias and Cu-Cu pads as the inter-wafer throughway. In our scheme, there are several reliability criteria, which include: (a) structural integrity of the Cu-Cu bond; (b) Cu-Cu contact electrical characteristics; and (c) process flow efficiency and repeatability. In addition, CAD tools are needed to aid in design and layout of 3DICs. This paper discusses recent results in all these areas.

Morphology and Bond Strength of Copper Wafer Bonding

The morphology and bond strength of copper-bonded wafer pairs prepared under different bonding/annealing temperatures and durations are presented. The interfacial morphology was examined by transmission electron microscopy while the bond strength was examined from a diesaw test. Physical mechanisms explaining the different roles of postbonding anneals at temperatures above and below 300°C are discussed. A map summarizing these results provides a useful reference on process conditions suitable for actual microelectronics fabrication and three-dimensional integrated circuits based on Cu wafer bonding.

Polysilicon thin-film transistors with channel length and width comparable to or smaller than the grain size of the thin film

Poly-Si thin-film transistors (TFTs) with channel dimensions (width W, and length L) comparable to or smaller than the grain size of the poly-Si film were fabricated and characterized. The grain size of the poly-Si film was enhanced by Si ion implantation followed by a low-temperature anneal and was typically 1 to 3 mu m in diameter. A remarkable improvement was observed in the device characteristics as the channel dimensions decreased to W=L=2 mu m. On the other hand, TFTs with submicrometer channel dimensions were characterized by an extremely abrupt switching in their I/sub D/ versus V/sub GS/ characteristics. The improvement was attributed to a reduction in the effect of the grain boundaries and to the effect of the devices floating body. >