Isamu Hanyu

High performance optical lithography using a separated light source

In projection lithography systems with fly’s‐eye elements, a virtual source is created as an array of approximately mutually incoherent point sources. This article describes light amplitude and phase simulations for an image of a mask illuminated by a point source. This article discusses the dependence on the point‐source location for a plane perpendicular to the optical axis. An image projected by a separated light source, rather than a ring‐shaped light source, improves due to interference effects between multiple apertures is shown. Resolution of 0.25 μm equal lines and spaces was improved experimentally at a wavelength of 365 nm and a numerical aperture of 0.54. Also, how an isolated pattern image can be improved theoretically using an optimally separated light source is shown.

Novel alternating phase-shift mask with improved phase accuracy

We developed an alternating phase shift mask that offers a sufficient phase accuracy for manufacturing sub-0.18 micrometer devices with 248 nm deep-UV lithography. This mask has a Cr/spin-on-glass/quartz structure. Our mask fabrication process utilizes some new techniques which include the use of a SOG shifter with extra thickness, a two step SOG etching, and an additional wet etchign process for phase adjustment. Our process showed a good performance, and a phase controllability of 180 plus or minus 0.7 degrees was achieved. Phase uniformity was less than 3 degrees over a 100 mm square area. It was nearly equal to the uniformity of the SOG thickness. These results prove that the additional etching process is very effective at improving phase accuracy.

Recent advances in ultrahigh-speed HEMT LSI technology

The current status of, and recent advances in, high electron mobility transistor (HEMT) technology for high-performance submicrometer VLSI are presented with a focus on materials, self-aligned device fabrication, and HEMT LSI implementation. The HEMT is a very promising device for ultrahigh-speed LSI/VLSI applications because of the high-mobility GaAs/AlGaAs heterojunction structure. The authors project an optimized chip delay of 40 ps at 10 K-gate VLSI at room temperature. >

A 40-ps high electron mobility transistor 4.1 K gate array

A high-electron mobility transistor (HEMT) 4.1 K-gate array has been developed, using a selective dry etching process and a MBE (molecular-beam epitaxy) growth technology. The circuit design uses direct-coupled FET logic (DCFL). The chip contains 4096 NOR gates, each with a 0.8- mu m gate length, and measures 6.3 mm*4.8 mm. A basic gate delay of 40 ps has been achieved. A 16*16-bit parallel multiplier, used to test this array, has a multiplication time of 4.1 ns at 300 K, where the power dissipation is 6.2 W. >

New phase-shifting mask with highly transparent SiO2 phase shifters

A phase-shifting mask enables subhalf-micron optical lithography. We propose a new phase-shifting mask with Si02 phase shifters. Si02 phase shifters on a quartz mask substrate have the advantages of low absorption under deep UV and a lack of multiple interference. Si02 phase shifters were fabricated by lift-off of the evaporated Si02 film. The new phaseshifting mask is highly transparent to deep UV and provides a 2 uniformity of phase shift over the full exposure field of a 5X stepper. Improved resolution of 0. 25 im lines and spaces was achieved by using a KrF excimer laser stepper and the new phase shifting mask. We also characterize the image profile projected with a phase-shifting mask because the reproducibility of mask features on a wafer declines when a phase-shifting mask is used. We indicate the importance of the interference between the main and side lobes of diffraction patterns for individual apertures and clarify the mechanism ofreproducibility degradation in optical lithography using a phase-shifting mask. 1.

Evaluation of chemically amplified resist based on adamantyl methacrylate for 193-nm lithography

An ArF single layer resist based on alicyclic polymer has been developed. Our work centers on improving the solubility of the base polymer in an aqueous base solution. The solubility is the most significant point in using alicyclic polymer. A suitable developer is obtained by adding isopropyl alcohol to the standard TMAH solution with a proper mixing ratio. This mixture greatly enhances the dissolution rate and allows the alicyclic polymer to act as a highly sensitive resist. Over-top coating has also been used to improve the pattern profile. We applied these processes to a resist based on a copolymer of 3-oxocyclohexyl methacrylate and adamantyl methacrylate. The results of ArF lithography are encouraging. There is a high sensitivity of about 10 mJ/cm2, and a high resolution of 0.17 micrometers lines and spaces is achieved. This shows that by enhancing the solubility the lithographic characteristics of the resist based on the alicyclic polymer are effectively improved.

Improving projection lithography image illumination by using sources far from the optical axis

In a projection lithography system having fly‐eye elements, a virtual source is created as an array of approximately mutually incoherent point sources. This paper describes simulated results of the light amplitude and phase of the mask‐projected image for a point source and discusses the dependence on the point source location on a plane situated perpendicular to the optical axis. We showed that the projected image illuminated by point sources far from the optical axis was improved by the effect of interference between multiple apertures. Resolution of the 0.4 μm lines and spaces was improved theoretically and experimentally at a wavelength of 435.8 nm and a numerical aperture of 0.45.

A 45 K-gate HEMT array with 35-ps DCFL and 50-ps BDCFL gates

A 45 K-gate emitter-coupled-logic (ECL)-compatible array with unbuffered and buffered direct-coupled FET-logic (DCFL and BDCFL) gates has been developed using 0.6- mu m-gate high-electron-mobility transistors (HEMTs) and four-level gold-based interconnects. The high-speed DCFL gates and more functional BDCFL gates are used to replace ECL macros efficiently. The basic cell, equivalent to four three-input NOR gates, consists of 12 enhancement-mode (E-mode) HEMTs, four depletion mode (D-mode) HEMTs, and two source-follower buffers. The basic gate delay times are 35 ps for 0.24-mW unbuffered DCFL gates and 50 ps for 0.38-mW BDCFL gates. The gate array chip is 9.8*9.8 mm and contains 45600 gates. The chip dissipates 11 W in 80% gate use. Silylated polymethyl silsequioxane (PMSS), which has a low dielectric constant of 3, is used for the interlayer dielectrics to reduce wiring delay. >

Practical method of evaluating two-dimensional resist features for lithographic DRC

The optical proximity effect becomes significant near the practical resolution limit of photolithography, depending on the wavelength and numerical aperture of the stepper. Recently, VLSI design rules have almost reached their limits. Larger ICs cannot be designed and be manufactured without using a lithographic DRC (design rule check) tool or an OPC (optical proximity correction) tool. Therefore, it has become necessary to develop a technology which can accurately predict resist features from the designed circuit layout. We studied deviation in both the line width and the length due to proximity effect and investigated the phenomena. Also we developed a technology which can accurately predict the behavior of the proximity effect from an aerial image. This technology is based on a simple threshold model. We optimized the calculations for an aerial image and the threshold of intensity in order to predict deviations in the line width and length. We also considered the profile of an aerial image to predict the critical point. The calculations for an aerial image and threshold which we optimized in this manner can be used to predict 2D patterns.

Simple Method of Correcting Optical Proximity Effect for 0.35 µm Logic LSI Circuits

We propose a practical optical proximity correction (OPC) system, whose characteristics are simple and effective, for logic LSI circuits and outline all the steps for OPC. We also report the improvement of gate length deviations in a logic device with OPC.