Isao Miyazaki

Quality Control And Diagnostic System For LSI Fabrication

Improving initial yield is one way to overcome the ever competitive market of semiconductors. To accomplish this, analyzing particle/pattern defects is a method in finding a countermeasure. We have developed a system, from controlling the master parameter setting, derive where and what the problem is. It gathers data from QC data; especially related to particles and pattern defects. This system is completely independent from other systems, thus enabling it to be used in any type of line(e.g. unautomated/automated, large/small.)

Failure rate estimation of each process layer using critical area analysis and failing bit results

We propose a novel method by which to accurately estimate the failure rate of each process layer on a wafer-by-wafer basis. In this method, we use the failing bit data and the results of critical area analysis (CAA) of each failing bit signature (FBS). We formulate the estimation as a linear programming model and convert the failure rate of each FBS to the failure rate of each process layer. A comparison of the failure rate estimated using this method and that obtained by test structure analysis reveals good agreement and the total estimation error of all process layers are within several percent. We also improved a legacy yield management system by implementing this estimation method. This system is used for failure analysis during semiconductor manufacturing. We show two case studies for 65 nm and 45 nm technology node products.

Advanced Method for Defect Characterization Using Fail Bit Analysis and Critical Area Simulation

We propose an advanced approach to accurately estimate wafer-wafer variation of random defect density in each process layer (<i>D</i>0_l) using fail bit analysis and critical area simulation. The proposed method formulates <i>D</i>0_l estimation using a linear programming model with constraint set of <i>D</i>0_l is positive. The <i>D</i>0_l estimation results are consistent with the test vehicles. We also illustrate some effective application results for yield improvement activities in the semiconductor manufacturing line.

Verification of Mask Manufacturing Load Estimation (MiLE)

The design shrinking of semiconductor devices and the pattern complexity generated after OPC (optical proximity correction) have an impact on the two major cost consuming processes in mask manufacturing, EB (electron beam) writing and defect assurance. Mask-DFM (design for manufacturing) is a technique with various steps ranging from the design to the mask manufacturing to produce the mask friendly designs and to reduce the workload in the advanced mask production. We have previously reported on our system, called MiLE (Mask manufacturing Load Estimation), which quantifies the mask manufacturing workload by using the results of mask layout analyses. MiLE illustrates the benefits of mask-DFM efforts as numerical indexes and accelerates the DFM approaches. In this paper, we will show the accuracy of the workload estimation of the advanced devices by the comparison between the indexes and the process times in the actual mask manufacturing. The throughput of MiLE calculation of the production masks of a 65nm device was measured.

OPC rule management system for SoC

We have developed a new document management system that aimed at change management of mask layout correction procedure that consists of OPC (Optical Proximity Correction) processing and lithography manufacturability checks in SoC (System on Chip) high-mix and small-quantity production. By systematically managing the OPC rule and the lithography manufacturability check result, we have eliminated mask correction troubles due to OPC management misled operation and lithography manufacturability check omission, and reduce the time of trouble solution of mask data correction originating.