Yuichi Hamamura

An advanced defect-monitoring test structure for electrical screening and defect localization

A new test structure for the detection and localization of short and open defects in large-scale integrated intralayer wiring processes is proposed. In the structure, an open-monitoring element in the first metal layer meanders around lines of short-monitoring elements placed in contact with N-type diffusion regions to make the structure compact. The proposed structure allows defective test structures to be screened through electrical measurements and killer defects to be localized through voltage contrast or optical microscopy methods.

Repair yield simulation with iterative critical area analysis for different types of failure

We propose a general method for repair yield estimation based on critical area analysis using a commercial Monte-Carlo simulator. We classify failures into several types according to the repair rules and use iterative critical area analysis for each type of failure (ICAA-ETF) to calculate the repair yield. Our proposed method makes it possible to accurately estimate within a few hours the repair yield of a memory product. An example of application to an actual SRAM product is discussed to illustrate in detail how our method can be used for critical area calculation and repair yield modeling.

An advanced defect-monitoring test structure for electrical measurements and defect localization

A new test structure for the detection and localization of short and open defects in LSI intra-layer wiring processes is proposed. In the structure, an open-monitoring element (OME) in the first metal layer meanders around lines of short-monitoring elements (SME) placed in contact with N-type diffusion regions to make the structure compact. The proposed structure allows defective test structures to be screened through electrical measurements and killer defects to be localized through voltage contrast or optical microscopy methods.

Failure rate estimation of each process layer using critical area analysis and failing bit results

We propose a novel method by which to accurately estimate the failure rate of each process layer on a wafer-by-wafer basis. In this method, we use the failing bit data and the results of critical area analysis (CAA) of each failing bit signature (FBS). We formulate the estimation as a linear programming model and convert the failure rate of each FBS to the failure rate of each process layer. A comparison of the failure rate estimated using this method and that obtained by test structure analysis reveals good agreement and the total estimation error of all process layers are within several percent. We also improved a legacy yield management system by implementing this estimation method. This system is used for failure analysis during semiconductor manufacturing. We show two case studies for 65 nm and 45 nm technology node products.

Advanced Method for Defect Characterization Using Fail Bit Analysis and Critical Area Simulation

We propose an advanced approach to accurately estimate wafer-wafer variation of random defect density in each process layer (<i>D</i>0_l) using fail bit analysis and critical area simulation. The proposed method formulates <i>D</i>0_l estimation using a linear programming model with constraint set of <i>D</i>0_l is positive. The <i>D</i>0_l estimation results are consistent with the test vehicles. We also illustrate some effective application results for yield improvement activities in the semiconductor manufacturing line.