Istvan Novak

Power distribution networks for system-on-package: status and challenges

The power consumption of microprocessors is increasing at an alarming rate leading to 2X reduction in the power distribution impedance for every product generation. In the last decade, high I/O ball grid array (BGA) packages have replaced quad flat pack (QFP) packages for lowering the inductance. Similarly, multilayered printed circuit boards loaded with decoupling capacitors are being used to meet the target impedance. With the trend toward system-on-package (SOP) architectures, the power distribution needs can only increase, further reducing the target impedance and increasing the isolation characteristics required. This paper provides an overview on the design of power distribution networks for digital and mixed-signal systems with emphasis on design tools, decoupling, measurements, and emerging technologies.

Lossy power distribution networks with thin dielectric layers and/or thin conductive layers

Through their inherent skin losses, conductive planes around sufficiently thin dielectric layers may provide good suppression of plane resonances in printed-circuit-board power distribution networks. When combined with thin conductive layers, a resistor-like flat self-impedance and low-pass transfer-impedance profiles can be created. A lossy transmission-line grid model is used to simulate power-ground plane pairs with thin dielectric and thin conductive layers. Some of the modeling errors of the analytical plane-impedance expressions and lossy transmission-line grid plane models are compared. Simulated and measured impedances are compared on test structures with plane separation of 40 and 8 /spl mu/m (1.6 and 0.3 mils).

Distributed matched bypassing for board-level power distribution networks

Power-distribution networks need to provide impedance response with specified shape/value over a wide frequency band. Bypass capacitors with different values, and capacitors and planes may create resonance peaks, unless the capacitor parameters are selected properly. Distributed matched bypassing (DMB) is suggested to create a smooth impedance profile. DMB requires components with Q/spl Lt/1, which in turn requires user-defined ESR. Different options are shown to set (increase) the ESR of bypass capacitors. The concepts of bypass quality factor (BQF) and bypass resistor (BR) are introduced.

Frequency-dependent characterization of bulk and ceramic bypass capacitors

Power distribution networks (PDN) use various kinds of capacitors to create the required impedance profile and to suppress noise. The simple model of bypass capacitors is a series R-L-C network with frequency independent parameters. The paper gives measured data for various bulk and ceramic capacitors, showing the extraction procedure and frequency dependent data of all three parameters. Various physical contributors to the frequency dependencies are identified. From low frequencies up to SRF (series resonance frequency), capacitance can drop as much as 60%. Inductance should be measured in a small PCB fixture with planes, vias and pads representing the intended application. The added inductance due to the capacitor body is shown to be fairly independent of via length connecting to the nearest planes.

Accuracy considerations of power-ground plane models

Power and ground planes in high-speed printed-circuit board stack-ups must be considered as two-dimensional transmission lines. In circuit simulations, the analytical expression of the plane impedance provides an easy means to compute the impedance at any arbitrary location. The expression of impedance contains a double infinite summation of modal harmonics which in practical calculations must be truncated. This paper discusses the effect of truncation, and it is shown that the summation limits should be set according to the dimensions and loss characteristics of the power-distribution planes.

Low impedance power planes with self damping

With the rapid increase of chip clock frequencies and power, the power distribution on printed-circuit boards must rely increasingly on power-ground plane pairs. The effects of dielectric thickness, dielectric constant, and parallel connection of power-ground plane pairs is discussed. It is shown that dielectric materials thinner than 0.5 mils naturally tend to suppress plane resonances.

ARIES: using annular ring embedded resistors to set capacitor ESR in power distribution networks

Power-distribution networks need to provide flat low impedance over a wide band. Bypass capacitors with different values, and capacitors and planes create resonance peaks, unless the capacitor parameters are selected properly. Distributed matched bypassing is used to create a smooth impedance profile. The ESR of ceramic capacitors is increased by adding embedded annular resistors in series to the capacitors.

Simulating complex power-ground plane shapes with variable-size cell SPICE grids

Power and ground planes can be simulated with rectangular uniform SPICE grids, or by analytically evaluating the double series of modal resonances. For nonrectangular shapes, the Transmission Matrix Method (TLM) can be used. For odd shapes, irregular outlines, cutouts and perforations, a variable-size cell grid is shown to be effective and sufficiently accurate. The adaptive grid preserves the static capacitance of the planes, calculates the modal resonances accurately in the presence of cutouts, and can also account for the perforations of planes.

Calculating partial inductance of vias for printed circuit board modeling

A complete derivation of inductance from energy relations is presented, outlining all the key steps and assumptions. Based on this derivation, the concept of partial inductance is reviewed and several useful expressions for partial inductance are presented. The accuracy of these expressions is then evaluated by comparing these formula to 3D field solutions and measurement data of test structures.

Modeling the impact of power/ground via arrays on power delivery

The impact of via arrays on power and ground planes is examined in This work. Measurements of the plane impedance were made on a 8/spl times/8 via array as a function of via pair location. The results from full-wave field solution are compared to measurement data and excellent correlation is obtained. The results show that the impedance and effective inductance is a strong function of location within the array. The lowest impedance and inductance is measured on the array perimeter. A 4 X increase in the impedance and inductance occurs at the array center. By parameterizing the antipad diameter in simulation it is found that the impedance increases sharply when the antipads overlap.