Larry D. Smith

Simultaneous switch noise and power plane bounce for CMOS technology

The simultaneous switch noise (SSN) problem has traditionally been thought of as an inductance problem. When many drivers on a Si chip switch at the same time, current crowds into the chip ground or V/sub dd/ inductance. Ground bounce occurs proportional to the inductance in the ground or V/sub dd/ lead and the rate of change of current. This line of thinking has been effective at solving SSN problems for lead frame packages. However, packaging has progressed to packages with power and ground planes. Package traces behave more like transmission lines with impedance and delay rather than lumped inductors. The signal waveform rise and fall times are so fast that an edge may fit within the package. Wire bonds have been replaced by solder bumps and peripheral leads have been replaced by solder balls. The new structures may have less than 1% of the inductance of the packages in use just a few years ago. Capacitive and resistive elements have been added to inductance matrices to account for the package time delay and losses, but the number of circuit elements in an SSN analysis and the increased number of simultaneously switching drivers have resulted in large, complex simulation runs that require much CPU time and computer resources. It has become harder to find meaningful model to hardware correlation for large SSN problems. It is time to consider a radically new approach to simulating the SSN problem. This paper looks at treatment of the SSN problem as a power plane bounce problem.

ESR and ESL of ceramic capacitor applied to decoupling applications

Power distribution system noise affects computer product timing performance, signal integrity and electromagnetic interference. Between 1 MHz and 1 GHz, the primary means of reducing power distribution noise is with ceramic decoupling capacitors. To achieve a certain target impedance, it is important to characterize the ESR of ceramic decoupling capacitors, as this directly determines the number of capacitors required on a board. A new technique to extract ESR is described in this paper. Another factor which determines the capacitance value of decoupling capacitors is the ESL (equivalent series inductance) associated with capacitors mounted on a PCB. A study that compares the ESL of different pad layout geometries is also presented.

Power plane SPICE models for frequency and time domains

A SPICE model for power plane simulation has been developed. It is based on the geometries and materials of the power planes and uses a unit cell composed of RLC elements, transmission line elements or the W-element. Important frequency and time domain properties are demonstrated through simulation, and model to hardware correlation is established in both domains.

A transmission-line model for ceramic capacitors for CAD tools based on measured parameters

An efficient and accurate transmission-line model for discrete MLC capacitors is developed. Hardware measurement techniques are used to obtain the circuit parameters for the model components. Low inductance measurement fixtures are required to observe and measure the transmission line parameters. The simulated impedance vs frequency results match closely with hardware measurements in the capacitance, resistance and inductance portions of the transfer impedance curve. The transmission-line model is well suited for CAD tools that are used to design power distribution systems.

Low impedance power planes with self damping

With the rapid increase of chip clock frequencies and power, the power distribution on printed-circuit boards must rely increasingly on power-ground plane pairs. The effects of dielectric thickness, dielectric constant, and parallel connection of power-ground plane pairs is discussed. It is shown that dielectric materials thinner than 0.5 mils naturally tend to suppress plane resonances.

Power distribution system for JEDEC DDR2 memory DIMM

The Power Distribution System (PDS) for a JEDEC DDR2 Dual Inline Memory Module (DIMM) has been designed. The process involved establishing a target impedance in the frequency domain, determining the inductance of the connector and capacitor mounts and selecting a matrix of discrete ceramic capacitors from a menu of previously characterized devices to meet the target impedance. After hardware was available, S21 measurements were made with a 2 port VNA to establish model to hardware correlation.

Power plane decoupling strategy for high speed processor boards

New generations of high speed processors are requiring more power. Consequently, in order to cope with the high amount of switching currents, efficient decoupling of power planes has become critical for both signal integrity (SI) and EMC. In this paper, an investigation has been conducted to find out the effects of decoupling capacitors on SI. A procedure for optimization of the decoupling capacitors based on the fundamental frequency and harmonic frequencies has been illustrated. The optimized decoupling strategy was then implemented on a dual processor board and was measured on a network analyzer. The authors have examined the effect of the decoupling strategy on SI.