Ittetsu Taniguchi

Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors

Systematic architecture exploration from vast solution space is a complex problem in embedded system design. It is very difficult to explore a best architecture fast and accurately because accurate evaluation usually consumes significant amount of time for point in the solution space. In this paper, we propose fast and systematic architecture exploration method for address generation unit (AGU) based on a coarse grained reconfigurable architecture model. First we prove that a set of Pareto solutions of cycle vs energy becomes a subset of Pareto solutions of cycle vs area under some practical assumptions. In addition we propose “Optimistic cycle (OC)” metric to find out promising solutions from vast solution space. Based on this metric we also propose a fast architecture exploration algorithm which only applies mapping to promising architectures. Using the proposed systematic architecture exploration method, we show that we can obtain almost the same trade-off points as the exhaustive search method and also that our method is about 164 times faster than exhaustive search.

Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model

In recent years, dynamic reconfigurable processor which can achieve reconfiguration with a few cycles is proposed. The fast reconfiguration makes run-time reconfiguration possible, and the run-time reconfiguration gives a new possibility to the dynamic reconfigurable processor, i.e. the dynamic reconfigurable processor can also execute partitioned independent subtasks with repeated reconfigurations and executions. However, to achieve an execution with the run-time reconfiguration, performance should be evaluated with various overheads: reconfiguration, memory accesses, etc. The overheads depend on reconfigurable architectures, and it is generally difficult to evaluate the overhead. As the overhead may critically affect the performance, designers should carefully explore design space for suitable architectures. In this paper, we propose a dynamic reconfigurable architecture exploration method based on Parameterized Reconfigurable Processor model (PRP-model) and task partitioning optimization algorithm for architecture exploration corresponding to proposed PRP-model. Experimental results showed that the proposed PRP-model and the task partitioning algorithm for PRP-model can fast evaluate various reconfigurable architectures, and designers can easily find suitable reconfigurable architectures by changing the PRPmodel parameters.

SSEST: Summer school on embedded system technologies

In recent years, embedded system technologies are evolving rapidly and in short-handedness of experienced engineers has become a serious problem. To solve this problem from the point of view of students and young engineers, a committee is organized by those members. We, the committee members, planned to provide a new educational material and a curriculum for students and young engineers to have an opportunity to learn embedded system technologies during summer time as summer school on embedded system technologies (SSEST). In this school, we aim to provide an education for basic knowledge and techniques about embedded systems through a whole development process and an interchange among people of different universities and companies through the processes. In this paper, we introduce the plan of summer school, and its educational material and the curriculum of SSEST in 2005 and 2006.

Soh aware battery management optimization on decentralized energy network

The battery degradation is serious problem for the modern electrical systems. This paper proposes State-of-Health (SoH) aware battery management optimization method on decentralized energy network. The power distribution problem is often solved with mixed integer programming (MIP), and proposed formulation takes into account the SoH model. Our poster shows the details and the effectiveness of proposed method.