Ivan Bastos

Automatic synthesis of RF front-end blocks using multi-objective evolutionary techniques

Typically the design of a Radio-Frequency (RF) circuit is difficult, time-consuming and often based around an iterative process. In this manuscript, an automatic synthesis of three typical blocks of nowadays RF front-end receivers, a narrowband differential low-noise amplifier, a mixer and a local oscillator, is presented. The synthesis of the three circuits was made at sizing level and was carried out by Analog IC Design Automation (AIDA). AIDA is a multi-objective multi-constraint simulator based automatic IC design tool, which optimizes analog circuits through the usage of evolutionary computation. The performance potential of the circuits and tool is evaluated through electrical simulation results, which are finally compared with recently published state-of-the-art works, with overall better results and little time-consumption, proving the surplus value of using an automatic IC design tool in RF circuitry synthesis. Automatic RF circuits sizing, using UMC 130 nm technologyMultiobjective multiconstraint simulator-based optimization approachProposal of a new LNA topology and complete description of the circuitsComplete description of the optimization flowCircuit evaluation using industrial simulators

Balun LNA with continuously controllable gain and with noise and distortion cancellation

In this paper we present a balun LNA with gain adjustable continuously by a voltage. The LNA is based on the combination of a common-gate and a common-source stage to cancel the noise and distortion of the common-gate stage. To obtain higher gain with the same DC voltage drop we replace resistors by PMOS transistors. This also allows continuous gain control and we show that by proper design, the effect on IIP3 and IIP2 can be neglected. With this approach, we avoid the use of switches, and the input impedance and the noise figure are not affected. Simulation results with a 130 nm CMOS technology show that the balun LNA has gain continuously tunable between 12 and 20 dB. The NF is below than 3.2 dB and the best IIP3 is higher than 0 dBm and the maximum IIP2 is 14 dBm. The total power dissipation is only 4.8 mW for a bandwidth of 5 GHz.

Noise canceling LNA with gain enhancement by using double feedback

In this paper we present a balun low noise amplifier (LNA) in which the gain is boosted by using a double feedback structure. The circuit is based on a conventional balun LNA with noise and distortion cancelation. The LNA is based on the combination of a common-gate (CG) stage and common-source (CS) stage. We propose to replace the load resistors by active loads, which can be used to implement local feedback loops (in the CG and CS stages). This will boost the gain and reduce the noise figure (NF). Simulation results, with a 130nm CMOS technology, show that the gain is 24dB and the NF is less than 2.7dB. The total power dissipation is only 5.4mW (since no extra blocks are required), leading to a figure-of-merit (FOM) of 3.8mW-1 using a nominal 1.2V supply. Measurement results are presented for the proposed DFB LNA included in a receiver front-end for biomedical applications (ISM and WMTS). HighlightsWe present a balun LNA with high gain and low noise figure by using active loads.A double feedback technique for gain enhancement and noise figure reduction is used.Two RF front-end receivers using a 130 nm CMOS technology were implemented: (1) using an LNA with active loads; (2) using an LNA with active loads and local double feedback.

A 1.2 V Low-Noise-Amplifier with Double Feedback for High Gain and Low Noise Figure

In this paper we present a balun low noise amplifier (LNA) in which the gain is boosted using a double feedback structure. The circuit is based in a conventional Balun LNA with noise and distortion cancellation. The LNA is based in two basic stages: common-gate (CG) and common-source (CS). We propose to replace the resistors by active loads, which have two inputs that will be used to provide the feedback (in the CG and CS stages). This proposed methodology will boost the gain and reduce the NF. Simulation results, with a 130 nm CMOS technology, show that the gain is 23.8 dB and the NF is less than 1.8 dB. The total power dissipation is only 5.3(since no extra blocks are required), leading to an FOM of 5.7 mW− 1 from a nominal 1.2 supply.