Blazej Nowacki

Design methodology for Sigma-Delta modulators based on a genetic algorithm using hybrid cost functions

The design of Sigma-Delta modulators (ΣΔMs) encompasses different variables that need to be optimized together in order to maximize the performance. The design task is even more complex due to the non-linear behavior of the quantizer. Typically, a linearized model of the quantizer is used to obtain linear equations that predict the performance of the modulator, which may cause significant discrepancies between the predicted and actual behavior of ΣΔMs. To better predict the behavior of a given design solution, we propose a design methodology for ΣΔMs based on a genetic algorithm (GA) that uses both linear equations and simulations: the design solution is evaluated using the equations and, if the performance is good enough, it will be evaluated trough simulation. This hybrid cost function allows to use a GA with a large population and, therefore, obtains the best possible design solution. The hybrid cost function takes thermal noise, quantization noise, voltage swing variations and stability of the modulator into account. Furthermore, it also selects the design solution that is the most insensitive to component variations. The design of a continuous-time (CT) and a discrete-time (DT) ΣΔM are given as proof-of-concept.

A 1.2 V 300 μW second-order switched-capacitor Δ∑ modulator using ultra incomplete settling with 73 dB SNDR and 300 kHz BW in 130 nm CMOS

This paper presents a Δ∑ modulator (Δ∑M) circuit based on the implementation of discrete time filters using ultra incomplete settling (UIS). This approach allows building a Δ∑M using mostly dynamic elements thus reducing the power dissipation. A prototyped 2nd-order Δ∑M circuit, using this technique, was designed in a 130 nm CMOS technology; the measured results prove the validity of the concept. Measured results show that the Δ∑M achieves a peak SNDR of 72.8 dB, a peak SNR of 73.9 dB and a DR of 78.2 dB for a signal with a bandwidth (BW) of 300 kHz, while dissipating less than 300 μW from a 1.2V power supply voltage, resulting in a FOM of 139.3 fJ/conv.-step. As far as the authors have knowledge, this circuit represents the first prototyped switched-capacitor (SC) circuit based on UIS.

A Fully Integrated and Reconfigurable Architecture for Coherent Self-Testing of High Speed Analog-to-Digital Converters

This paper presents a reconfigurable architecture for coherent built-in self-testing (BIST) of high speed analog-to-digital converters (ADCs) with moderate resolutions. The proposed system is suited to be fully integrated with the ADC and, besides a low jitter clock reference, no other external high quality generators are required. The complete system comprises two synchronized phase-locked loops (PLLs), one based on a two-integrator oscillator capable of providing low distortion outputs and another based on a relaxation oscillator providing low jitter squared output, to allow coherent sampling. A detailed description of the building blocks of both PLLs is given as well as the techniques used to minimize area of the loop filters (LFs), to stabilize the output amplitude of the two-integrator oscillator to a known value, and to improve the total harmonic distortion (THD) of this oscillator. Post-layout simulations, in a 0.13 μm CMOS technology, of the proposed BIST scheme applied to a case-study 6-bit 1 GS/s ADC are shown and validate the proposed test methodology.

A second-order switched-capacitor ΔΣ modulator using very incomplete settling

This paper presents a novel ΔΣ circuit based on the implementation of discrete time filters using very incomplete settling. This approach allows building a ΔΣM with mostly dynamic elements thus reducing the power dissipation. A 2nd order ΔΣM architecture, using this technique, is presented and analyzed. High-level and transient noise electrical simulations prove the validity of the concept. Electrical simulations show that the ΔΣM achieves a peak SNDR of 74.0 dB, a peak SNR of 78.6 dB and a dynamic range of 82.4 dB for a signal with a bandwidth of 300 kHz, while dissipating 204 µW from a 1.1 V power supply voltage, indicating that, a FOM of 174 dB can be reached.

Fully integrated and reconfigurable architecture for coherent self-testing of IQ ADCs

In this paper we present a reconfigurable architecture for coherent built-in self-testing (BIST) of high speed IQ ADCs with moderate resolutions. The proposed system can be fully integrated with the ADC and, besides a low-jitter clock reference, no other external high quality generators are required. A locked system comprising a first phase-locked loop (PLL) with two IQ linear outputs and a second PLL with a squared output signal are proposed as well as the dedicated voltage-controlled oscillator (VCO) circuits. To illustrate the simplicity of the proposed solution, the system is designed, parameterized and simulated targeting the BIST of a 6-bit 1 GS/s ADC.

A low power 4 th order MASH switched-capacitor ΣΔ modulator using ultra incomplete settling

A discrete-time, switched-capacitor, MASH 2-2 4th order ΣΔ modulator, clocked with frequency of 1 GHz, was designed in a 65 nm CMOS technology. This modulator uses passive integrators based on the ultra-incomplete settling (UIS) concept. Electrical simulations show that the modulator achieves a peak SNDR of 66.8 dB, a peak SNR of 67.7 dB, an ENOB of 10.8 bits and DR of 70dB for a signal with a bandwidth of 10 MHz, while dissipating 1.5 mW from a 1.1 V power supply voltage, indicating that, a FOM of 42.7 fJ/conv.-step can be reached.

15.3 A 1V 77dB-DR 72dB-SNDR 10MHz-BW 2-1 MASH CT ΔΣM

ΔΣM performance can be improved by using MASH or SMASH structures to obtain higher-order noise shaping [1]. They have better stability than single-loop structures. The power dissipation of ΔΣMs can be reduced by using simpler amplifiers such as single-stage or inverter-based amplifiers [2]. Selecting a passive or active-passive ΔΣM architecture, where the processing gain of comparator is used in the feedback loop of the ΔΣMs filter [3], allows a reduction in the number of amplifiers and their gain. This solution is very appealing for deep-nanometer CMOS technologies, because a comparator can achieve large gain through positive feedback, which improves with faster transistors. This paper presents a passive-active CT 2-1 MASH ΔΣM using RC integrators, low-gain stages (~20dB) and simplified digital cancellation logic (DCL). The ΔΣM, clocked at 1GHz, achieves DR/SNR/SNDR of 77/76/72.2dB for input signal BW of 10MHz, while dissipating 1.57mW from a 1V supply.