Ivan Beretta

A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design

Nowadays, multi-core systems-on-chip (SoCs) are typically required to execute multiple complex applications, which demand a large set of heterogeneous hardware cores with different sizes. In this context, the popularity of dynamically reconfigurable platforms is growing, as they increase the ability of the initial design to adapt to future modifications. This paper presents a design flow to efficiently map multiple multi-core applications on a dynamically reconfigurable SoC. The proposed methodology is tailored for a reconfigurable hardware architecture based on a flexible communication infrastructure, and exploits applications similarities to obtain an effective mapping. We also introduce a run-time mapper that is able to introduce new applications that were not known at design-time, preserving the mapping of the original system. We apply our design flow to a real-world multimedia case study and to a set of synthetic benchmarks, showing that it is actually able to extract similarities among the applications, as it achieves an average improvement of 29% in terms of reconfiguration latency with respect to a communication-oriented approach, while preserving the same communication performance.

A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices

The automatic generation of hardware implementations for a given algorithm is generally a difficult task, especially when data dependencies span across multiple iterations such as in iterative stencil loops (ISLs). In this paper, we introduce an automatic design flow to extract parallelism from an ISL algorithm and perform a design space exploration to identify its best FPGA hardware implementation, in terms of both area and throughput. Experimental results show that the proposed methodology generates hardware designs whose performance is comparable to the one of manually-optimized solutions, and orders of magnitude higher than the implementations generated by commercial high-level synthesis tools.

B²IRS: A Technique to Reduce BAN-BAN Interferences in Wireless Sensor Networks

Wireless Sensor Networks (WSNs) are particular networks characterized by limited energy and computational resources and, if their transmission range is limited to a persons area, they are known as Body Area Networks (BANs). When two or more BANs are co-located and operate on the same channel, active periods can overlap and transmissions can conflict. This phenomenon, that drastically reduces performances and reliability of BANs, is known as BAN-BAN interference. In order to solve this issue, it is possible to employ techniques such as channel switching. However, channel switching is not suitable if the amount of channels is lower than the amount co-located BANs and, considering that interferences of Zigbee/802.15.4 networks with other technologies like 802.11 or Bluetooth reduce the amount of channels available for communication, an alternative approach is required. This paper introduces a BAN-BAN Interference Reduction System (B2IRS) which reschedules beacon packets in order to avoid active period overlap, reducing the interferences between distinct BANs. This approach is complementary to channel switching since it works with single-channel interferences, that arise when no free channels are available anymore. Experimental results, conducted comparing our methodology with the original IEEE 802.15.4, show that B2IRS is able to effectively reduce BAN-BAN interference, making it possible to almost maintain the same performance and energy consumption of an ideal situation (without interferences).

Hardware/software approach for code synchronization in low-power multi-core sensor nodes

Latest embedded bio-signal analysis applications, targeting low-power Wireless Body Sensor Nodes (WBSNs), present conflicting requirements. On one hand, bio-signal analysis applications are continuously increasing their demand for high computing capabilities. On the other hand, long-term signal processing in WBSNs must be provided within their highly constrained energy budget. In this context, parallel processing effectively increases the power efficiency of WBSNs, but only if the execution can be properly synchronized among computing elements. To address this challenge, in this work we propose a hardware/software approach to synchronize the execution of bio-signal processing applications in multi-core WBSNs. This new approach requires little hardware resources and very few adaptations in the source code. Moreover, it provides the necessary flexibility to execute applications with an arbitrarily large degree of complexity and parallelism, enabling considerable reductions in power consumption for all multi-core WBSN execution conditions. Experimental results show that a multi-core WBSN architecture using the illustrated approach can obtain energy savings of up to 40%, with respect to an equivalent single-core architecture, when performing advanced bio-signal analysis.

Model-based design for wireless body sensor network nodes

Wireless body sensor networks (WBSNs) are a rising technology that allows constant and unobtrusive monitoring of the vital signals of a patient. The configuration of a WBSN node proves to be critical in order to maximize its lifetime, while meeting the predefined performance during signal sensing, preprocessing, and wireless transmission to the base station. In this work, we propose a model-based optimization framework for WBSN nodes, which is centered on a detailed analytical characterization of the most energy-demanding components of this application domain. We also propose a multi-objective exploration algorithm to evaluate the node configurations and the corresponding performance tradeoffs. A case study is discussed to validate the proposed framework, proving that our model captures the behavior of real WBSNs and efficiently leads to the determination of the Pareto-optimal configurations.

A Hybrid Mapping-Scheduling Technique for Dynamically Reconfigurable Hardware

Reconfigurable computing is a promising technology that offers an interesting trade-off between flexibility and performance, which many recent multi-core embedded system applications demand. In order to achieve these objectives, it is necessary to optimize the deployment of the hardware cores on the FPGA platform, trying to reduce the reconfiguration overhead while meeting the desired performance. In this paper, we propose a hybrid mapping and scheduling technique for multi-core applications on reconfigurable devices, which exploits the information about the relationships among the application cores to minimize the overhead due to reconfiguration.

A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms

Reconfigurable platforms are a promising technology that offers an interesting trade-off between flexibility and performance, which many recent embedded system applications demand, especially in fields such as multimedia processing. These applications typically involve multiple ad-hoc tasks for hardware acceleration, which are usually represented using formalisms such as Data Flow Diagrams (DFDs), Data Flow Graphs (DFGs), Control and Data Flow Graphs (CDFGs) or Petri Nets. However, none of these models is able to capture at the same time the pipeline behavior between tasks (that therefore can coexist in order to minimize the application execution time), their communication patterns, and their data dependencies. This article proves that the knowledge of all this information can be effectively exploited to reduce the resource requirements and the timing performance of modern reconfigurable systems, where a set of hardware accelerators is used to support the computation. For this purpose, this article proposes a novel task representation model, named Temporal Constrained Data Flow Diagram (TCDFD), which includes all this information. This article also presents a mapping-scheduling algorithm that is able to take advantage of the new TCDFD model. It aims at minimizing the dynamic reconfiguration overhead while meeting the communication requirements among the tasks. Experimental results show that the presented approach achieves up to 75% of resources saving and up to 89% of reconfiguration overhead reduction with respect to other state-of-the-art techniques for reconfigurable platforms.

A Wireless Body Sensor Network for Activity Monitoring with Low Transmission Overhead

Activity recognition has been a research field of high interest over the last years, and it finds application in the medical domain, as well as personal healthcare monitoring during daily home- and sports-activities. With the aim of producing minimum discomfort while performing supervision of subjects, miniaturized networks of low-power wireless nodes are typically deployed on the body to gather and transmit physiological data, thus forming a Wireless Body Sensor Network (WBSN). In this work, we propose a WBSN for online activity monitoring, which combines the sensing capabilities of wearable nodes and the high computational resources of modern smart phones. The proposed solution provides different tradeoffs between classification accuracy and energy consumption, thanks to different workloads assigned to the nodes and to the mobile phone in different network configurations. In particular, our WBSN is able to achieve very high activity recognition accuracies (up to 97.2%) on multiple subjects, while significantly reducing the sampling frequency and the volume of transmitted data with respect to other state-of-the-art solutions.

On-line task management for a reconfigurable cryptographic architecture

The increasing amount of programmable logic provided by modern FPGAs makes it possible to execute multiple hardware applications on the same device. This approach is reinforced by dynamic reconfiguration, which allows a single part of the device to be configured with a single hardware module. The proposed solution is a Linux-based operating system to manage on-demand module configuration on an FPGA while providing a set of high-level abstractions to user applications. The proposed approach has been validated in a cryptographic context using the DES and the AES algorithms.

Knowledge-based design space exploration of wireless sensor networks

The complexity of Wireless Sensor Networks (WSNs) has been constantly increasing over the last decade, and the necessity of efficient CAD tools has been growing accordingly. In fact, the size of the design space of a WSN has become large, and an exploration conducted by using semi-random algorithms (such as the popular genetic or simulated annealing algorithms) requires an unacceptable amount of time to converge due to the high number of parameters involved. To address this issue, in this paper we introduce a knowledge-based design space exploration algorithm for the WSN domain, which is based on a discrete-space Markov decision process (MDP). In order to enhance the performance of the proposed algorithm and to increase its scalability, we tailor the classical MDP approach to the specific aspects that characterize the WSN domain. We exploit domain-specific knowledge to choose the best node-level configuration in WSNs using slotted star topology in order to reduce the exploration time. The proposed approach has been tested on IEEE 802.15.4 star networks with various configurations of the number of nodes and their packet rates. Experimental results show that the proposed algorithm reduces the number of simulations required to converge, with respect to state-of-the-art algorithms (e.g., NSGA-II, PMA and MOSA), from 60 to 87%