A.H.M. van Roermund

General current-mode analysis method for translinear filters

Log-domain or translinear filters are regarded as being a promising alternative in the area of low-voltage filter design. To date, most publications have reported on synthesis of translinear filters. Although synthesis is more powerful than analysis, it must go together with a generally applicable analysis method in the same domain. In this paper, a general current-mode analysis method is proposed. By using a current-mode approach, we stay close to the existing theory on static translinear circuits, which might be beneficial in developing a general, possibly more powerful synthesis method.

Analysis and design of high-performance asynchronous sigma-delta Modulators with a binary quantizer

Asynchronous sigma-delta modulators (ASDMs) are closed-loop nonlinear systems that transform the information in the amplitude of their input signal into time information in the output signal, without suffering from quantization noise such as in synchronous sigma-delta modulators. This is an important advantage with many interesting applications. In contrast with their synchronous counterparts, ASDMs have been underexposed. Both conceptually and analytically, they are quite complex. This paper investigates in detail the analysis, design and circuit-implementation aspects of ASDMs with a binary quantizer. In the ASDM, the amplitude-time transformation is done using an inherent self-oscillation denoted as a limit cycle. The oscillation frequency is addressed as the main design parameter that determines the spectral properties of the ASDMs and the quality of the amplitude-time transformation. Analytical and graphical derivations of the limit cycle frequency are treated. The impact of the filter order and the properties of the nonlinear element are elaborated on. Circuit implementations and the tradeoffs in the design are presented for a first- and a second-order ASDM that target the VDSL front-end specifications. Prototypes are implemented in a digital 0.18-/spl mu/m 1.8-V CMOS technology. The measured SFDR is 75dB in a frequency band of 8MHz for the first-order ASDM, and 72dB in a band of 12MHz for the second-order ASDM. The dissipated power is 1.5 mW and 2.2 mW, respectively.

A continuous-time /spl Sigma//spl Delta/ ADC with increased immunity to interferers

Receivers are being digitized in a quest for flexibility. Analog filters and programmable gain stages are being exchanged for digital processing at the price of a very challenging ADC. This paper presents an alternative solution where the filter and programmable gain functionality is integrated into a /spl Sigma//spl Delta/ ADC. The novel filtering ADC is realized by adding a high-pass feedback path to a conventional /spl Sigma//spl Delta/ ADC while a compensating low-pass filter in the forward path maintains stability. As such, the ADC becomes highly immune to interferers even if they exceed the maximum allowable input level for the wanted channel. As a consequence, the ADC input range can be programmed dynamically to the level of the wanted signal only. This results in an input-referred dynamic range of 89 dB in 1-MHz bandwidth and an intentionally moderate output signal-to-noise-and-distortion ratio of 46-59 dB (depending on the programmed gain). The merged functionality enables a better overall power/performance balance for the receiver baseband. The design consumes less than 2 mW and active area is 0.14 mm/sup 2/ in a 0.18-/spl mu/m digital CMOS technology.

An RMS-DC converter based on the dynamic translinear principle

Translinear or log-domain filters are theoretically exact realisations of linear differential equations. However, the dynamical translinear principle can also be applied to the implementation of nonlinear differential equations. In this paper, an RMS-DC converter is proposed, comprising a direct implementation of the corresponding nonlinear differential equation by means of the dynamical translinear principle. Correct operation of the circuit was verified through measurements.

A 60GHz digitally controlled phase shifter in CMOS

This paper presents a 60 GHz digitally controlled phase shifter in the 65 nm CMOS technology. Using a differential varactor-loaded transmission-line architecture, the phase shifter achieves a phase resolution of 22.5deg, an average insertion loss of 8.5 to 10.3 dB and a return loss of better than 10 dB from 55 to 65 GHz. The phase shifter occupies an area of only 0.2 mm2. To the knowledge of the authors, this is the first 60 GHz digitally controlled phase shifter with a phase resolution of 22.5deg in silicon reported to date. It is well suited for a 60 GHz phased array.

A low-voltage ultra-low-power translinear integrator for audio filter applications

In this paper, the design and measurement of a l-V translinear integrator and its application in a controllable second-order lowpass filter for hearing instruments is presented. A semicustom version of the filter has been integrated in a standard 2-/spl mu/m, 7-GHz, bipolar IC process and operates at voltages down to 1 V, consumes only 6 /spl mu/A, and has a dynamic range of 57 dB for a total harmonic distortion below 2%. Its cutoff frequency is linearly adjustable in octaves from 1.6 to 8 kHz.

An optimally coupled 5 GHz quadrature LC oscillator

A 5 GHz quadrature LC oscillator is realized which is based on a new architecture for multi-phase LC oscillators. Each section in the oscillator is coupled with an explicit phase shift of 180 degrees divided by the number of sections. Analysis on behavioral level shows that this maximizes the quality factor, and as a result, the carrier-to-noise ratio and robustness. An effective quality factor is derived which quantizes the degradation in phase noise performance if the sections of a multiphase LC oscillator are non-optimally coupled. The realized 5 GHz quadrature LC oscillator demonstrates that even at high frequencies the additional complexity of the proposed architecture yields a CNR improvement. The oscillator is realized in a BiCMOS process with a cut-off frequency of 30 GHz using an LC resonator with a quality factor of 4. A tuning range from 4.91 to 5.23 GHz is obtained with a CNR better than 113 dBc/Hz at 2 MHz offset. The VCO core power dissipation is only 21.2 mW at 2.7 V supply voltage.

A CMOS V-I converter with 75-dB SFDR and 360-/spl mu/W power consumption

This work describes a method for analysis of voltage-to-current converters (V-I converters or transconductors) and a novel V- I converter circuit with significantly improved linearity. The new circuit utilizes a combination of cross-coupling and local resistive feedback for a significant, simultaneous suppression of the third- and fifth-order harmonic distortion components in the transconductor characteristics. An evaluation of the optimal circuit dimensioning is shown. Simple and robust design rules are derived for the chosen operation conditions. The transistor implementation is presented and a prototype V- I converter is realized in a digital 0.18-/spl mu/m CMOS technology. The measured spurious-free dynamic range is 75 dB in a frequency band of 10 MHz. The circuit occupies less than 0.02 mm/sup 2/ and dissipates 360 /spl mu/W.

A 3 mW 54.6 GHz Divide-by-3 Injection Locked Frequency Divider With Resistive Harmonic Enhancement

A 54.6 GHz divide-by-3 injection locked frequency divider with low power consumption is presented. A resistive feedback is implemented to achieve a stable dc input and higher injection efficiency. Compared with the conventional design, it exhibits a better supply voltage rejection and wider locking range while a small silicon area is maintained. Fabricated in a TSMC 65 nm bulk CMOS process, this divider operates from 48.8 to 54.6 GHz and consumes 3 mW from a 0.9 V supply.

A 12b 500MS/s DAC with >70dB SFDR up to 120MHz in 0.18μm CMOS

A CMOS current steering 12b 500MS/s 216mW DAC without any additional circuitry to remove errors introduced during the conversion process has >70dB SFDR up to 120MHz above the Nyquist band. This is comparable to state-of-the-art performance requiring additional circuitry, and better than any design without additional circuitry