J. Auersperg

Characterization of dual-stage moisture diffusion, residual moisture content and hygroscopic swelling of epoxy molding compounds

Experimental and FEM studies have been undertaken in order to characterize the non-Fickian behavior of moisture absorption, temperature-dependent residual moisture content and hygroscopic swelling of epoxy molding compounds exposed to moist environments. Moisture absorption and desorption tests of two molding compounds and two IC packages using these materials have been carried out by gravimetric methods. Finite element analysis has been performed to simulate the anomalous dual-stage moisture absorption. To consider the residual moisture remaining in the package after the desorption process, a simple method has been developed, which allows for consideration of bake-out conditions and provides much more flexibility, enabling calculation of the non-Fickian moisture desorption with a specific residual moisture content. The coefficient of moisture expansion (CME) has been also measured by coupling the results of thermal mechanical analyzer (TMA) and Thermal Gravitational Analyzer (TGA) at different temperatures. It has been shown that the moisture desorption model of this study can be used as an alternative for TGA.

Fracture mechanics based crack and delamination risk evaluation and RSM/DOE concepts for advanced microelectronics applications

Fatigue and failure of advanced electronic packages and related systems is often caused by their increasing use under harsh environmental conditions - extreme temperatures, in particular. As a result, its thermomechanical reliability becomes more and more one of the most important preconditions for adopting it in industrial applications. Residual stresses from several steps of the manufacturing process, thermal and static and dynamic mechanical loading conditions along with the fact that microelectronic packages are basically compounds of materials with quite different Youngs modules and thermal expansion coefficients contribute to interface delamination, chip cracking and fatigue of interconnects. Consequently, numerical investigations by means of nonlinear parameterized FEA, fracture mechanics concepts are frequently used for design optimizations using sensitivity analyses (Auersperg et al., 2001). So, numerical design studies can help to optimize designs of electronics applications at the earlier phase of the product development processes. Unfortunately, this methodology typically accounts for classical stress/strain evaluation or life-time estimations of solder interconnects using modified Coffin-Manson approaches. Delamination or bulk fracture mechanisms usually remain unconsidered. This contribution intends to figure out and discuss ways of using fracture mechanics numerical approaches in connection with parameterized FEA based DOE/RSM. For improving such methods, the evaluation of mixed mode interface delamination phenomena of several ceramics/encapsulant-specimens under bending has been combined with experimental deformation measurements. Measured force vs. deflection curves, deformation fields as results of optical inspection and deformation analysis as well as crack tip vs. deflection curves determined using constitute the input for the delamination modeling by means of FEM. Major goal of the study is to make such a way determined interface toughness parameters applicable within DOE/RSM-approaches.

Stress analyses of high spatial resolution on TSV and BEoL structures

Abstract Knowledge and control of local stress development in Back-End-of-Line (BEoL) stacks and nearby Through Silicon Vias (TSVs) in advanced 3D integrated devices is a key to their thermo-mechanical reliability. The paper presents a combined simulation/measurement approach to evaluate stresses generated in the result of the TSV and BEoL stack manufacturing and 3D bonding processes. Stress measurement methods of high spatial resolution capability (microRaman and Focused Ion Beam (FIB) based stress release techniques) are used to obtain stress data from real components as manufactured. Finite Element Analysis (FEA) allows a more accurate interpretation of measurements results as well as a subsequent comprehensive analysis of failure behaviour. The paper gives an introduction to the applied local stress measurement on advanced multi-layer systems and 3D integration components referring to the state-of-art capabilities and limitations. The need of experimental stress data generation is illustrated on FEA examples. Illustration is given for FEA applications on 3D IC integration components currently lacking appropriate residual stress input for an assumed initial state.

Interaction integral and mode separation for BEoL-cracking and -delamination investigations under 3D-IC integration aspects

As a consequence of increasing functional density and miniaturization in microelectronics new low-k and ultra-low-k materials are going to be increasingly used in Back-end of line (BEoL) layers of advanced CMOS technologies. These ongoing trends together with the transition to the use of TSVs for 3D-IC-integration cause novel challenges for reliability analysis and prediction of relevant electronics assemblies. The optimization of fracture and fatigue resistance of those BEoL structures under manufacturing/packaging (during lead-free reflow-soldering, in particular) as well as chip package interaction (CPI) aspects is a key for further enhancements - see also [1]. In particular in this context the evaluation of the risk of delamination at bi-material interfaces and damaging and cracking of materials needs to be improved. The application of advanced finite element techniques combined with experimental observations and validations, provide a way to gain more fundamental knowledge and ultimately, to understand, predict and prevent reliability issues. However, cracking and delamination risk evaluations hang behind the needs - especially for nonlinear, transient, thermal loading of bi-material interface fracture. At this point, the correct mode mixity separation at bi-material interface cracks is a precondition for proper delamination risk evaluation. However, different approaches are known to be dependent on mesh density, integration path and/or reference length. We discuss the use of VCCT and integral fracture concepts for bulk and bi-material interface fracture in multi-scale and multi-failure modeling approaches. Energy release rate (ERR), stress intensity factors (SIF) and the related phase angles as results of the different approaches will be investigated and compared. Analytic relations between them will be pointed out and verified. Therefore, the frequently investigated role of reference length, normalizing length and path dependence for the calculation of the fracture parameters is discussed. Effects on the fracture parameters are finally discussed related to the cracking risk of BEoL structures. The authors combine these numerical approaches with experimental results in order to optimize the toughness for bulk material fracture and interface delamination with regard to structural modifications.

Crack and damage in low-k BEoL stacks under assembly and CPI aspects

Miniaturization and increasing functional integration as the electronic industry drives push the development of feature sizes down to the nanometer range. Moreover, harsh operational conditions and new porous or nano-particle filled materials introduced on both chip and package level - low-k and ultra low-k materials in Back-end of line (BEoL) layers of advanced CMOS technologies, in particular - cause new challenges for reliability analysis and prediction. The authors show a combined numerical/experimental approach and results towards optimized fracture and fatigue resistance of those BEoL structures under manufacturing/packaging (during lead-free reflow-soldering, in particular) as well as chip package interaction (CPI) aspects by making use of bulk and interface fracture concepts, in multi-scale and multi-failure modeling approaches with several kinds of failure/fatigue phenomena. Probable crack paths and interactions between material damaging and interface fracture will be investigated and sensitivities with regard to structural modifications studied. Complementary to the simulation side of reliability estimations, serious issues are connected with the collection of appropriate material properties in the miniaturized range addressed - Youngs modulus, initial yield stress, hardening. Nano-indentation, AFM, FIB and EBSD provide these desired properties, in particular. In addition, manufacturing induced residual stresses in the Back-end layer stack have an essential impact on damage behavior, because they superpose functional and CPI loads. Their determination with a spatial resolution necessary for typical BEoL structure sizes is a critical issue. The nano-scale stress relief technique (fibDAC) makes use of tiny trenches placed with a focused ion beam (FIB) equipment at the position of stress measurement. Digital image correlation algorithms applied to SEM micrographs captured before and after ion milling allows to conclude on stresses released. Residual stresses can be computed with the help of appropriate, adjusted FEA models.

FibDAC - Residual Stress Determination by Combination of Focused Ion Beam Technique and Digital Image Correlation

New challenges for design, manufacturing and packaging of MEMS/NEMS arise from the ongoing miniaturization process. Therefore there is a demand on detailed information on thermo-mechanical material properties of the applied materials. Because of size effects and the strong dependency of the thermo-mechanical behavior of active and passive components on process parameters often unsolved questions of residual stresses lead to system failure due to crack formation. With the fibDAC (Focused Ion Beam based Deformation Analysis by Correlation) method which is presented in this paper the classical hole drilling method for stress release measurement has been downscaled to the nanoscale. The ion beam of the FIB station is used as a milling tool which causes the stress release at silicon microstructures of MEMS devices. The analysis of the stress release is achieved by digital image correlation (DIC) applied to load state SEM images captured in a cross beam equipment (combination of SEM and FIB). The results of the DIC analysis are deformation fields which are transferred to stress solution by application of finite element analysis. In another step the resolution of the method has been improved by the application of trench milling instead of hole milling. Thereby deformation measurements in the nm range are established. The method is also a powerful tool for the analysis of sub-grain stresses of engineering materials.

Parametric Approach to Numerical Design for Optimization of Stacked Packages

The main aim for development of smaller packages is mainly due to ongoing development of portable communications devices. Thin silicon die improves device performance and reliability. Novel technological processes allow for the thinning of wafers to 2 mils without residual damage to the backside silicon or topside circuitry. Stacked packages reduce packaging cost and cycle-times. Wafers are stacked to form 3D multi-chip packages. On the other hand the electronic market requires novel and efficient designing tools as numerical design for optimization. The goal of the work was to design a reliable numerical model of the stacked package and afterwards perform numerical design for optimization in reference to a number of variables, which influence the package reliability. The numerical model of the analyzed stacked package was elaborated in ABAQUS with an embedded Python script language. The design for optimization was done by two alternative approaches: direct and indirect design for optimization. The direct approach was based on genetic algorithms while indirect approach was achieved by combination of design of experiments (DOE) with response surface modeling (RSM) methods

Combined Fracture, Delamination Risk and Fatigue Evaluation of Advanced Microelectronics Applications towards RSM/DOE Concepts

Microelectronic assemblies are basically compounds of several high precision materials with quite different Youngs moduli and thermal expansion coefficients (CTE). Additionally, various kinds of inhomogeneity, residual stresses generated by several steps of the manufacturing process and extreme thermal environmental conditions contribute to interface delamination, chip cracking and fatigue of solder interconnects. For that reason, numerical investigations by means of nonlinear FEA together with conventional strength hypotheses are frequently used for design optimizations and sensitivity analyses. So, design studies on the basis of parameterized FE-models and DOE/RSM-approaches help to optimize electronic components at early phases of the product development process. But, this methodology typically bases on classical stress/strain strength evaluations or/and life time estimations of solder interconnects using modified Coffin-Manson approaches, whereas delamination or bulk fracture mechanisms usually remain unconsidered. By means of a representative microelectronics assembly this contribution is going to figure out and discuss ways and challenges of using numerical fatigue evaluation and fracture mechanics approaches in connection with parameterized finite element modeling based DOE/RSM-concepts. That is, the evaluation of mixed mode interface delamination phenomena utilizing the VCCT-methodology, classical strength hypotheses along with fracture mechanics approaches and modified Coffin-Manson thermal fatigue estimation of solder joints will be simultaneously applied within a multi-objective optimization towards a thermo-mechanical reliable design

On the crack and delamination risk optimization of a Si-interposer for LED packaging

3D-integration becomes more and more an important issue for advanced LED packaging solutions as it is a great challenge for the thermo-mechanical reliability to remove heat from LEDs to the environment by heat spreading or specialized cooling technologies. Thermal copper-TSVs provide an elegant solution to effectively transfer heat from LED to the heat spreading structures on the backside of a substrate. But, the use of copper-TSVs generates also novel challenges for reliability as well as also for reliability analysis and prediction, i.e. to manage multiple failure modes acting combined - interface delamination, cracking and fatigue, in particular. In this case, the thermal expansion mismatch between copper and silicon yields to risky stress situations. Therefore, the authors performed extensive simulative work to overcome cracking and delamination risks in the vicinity of thermal copper-TSVs by means of fracture mechanics approaches. Especially, an interaction integral approach is utilized within a simulative DoE and X-FEM is used to help clarifying crack propagation paths in silicon. The DoE-based response surface methodology provided a good insight into the role of model parameters for further optimizations of the intended thermal TSV-approaches in LED packaging applications.

Damage and fracture evaluation in microelectronic assemblies by FEA and experimental investigations

Thermomechanical reliability of electronic packaging such as flip chip and chip scale packaging is most important for adoption of these technologies in industrial applications. However, various kinds of inhomogeneities, localized stresses and thermal mismatch between several components lead to interface delaminations, chip cracking and solder interconnect fatigue. Nonlinear finite element simulations which respect the nonlinear, temperature and rate dependent behaviour of different materials used (metals, polymeric and solder materials) and experimental investigations have been used for failure analysis. The development and application of failure models (e.g. thermal fatigue, lifetime prediction by Coffin-Manson type equations, integral fracture mechanics approaches such as J-, J/spl circ/-, and /spl Delta/T*-integral, and evaluation of critical regions) is explained. The influence of the scatter of some model parameters is investigated by probabilistic failure concepts. Additionally, simulation of damage growth in solder interconnects by an automatic adaptive finite element technique is performed using inherent local damage models to validate crack and damage models used. Consequently, some results have been compared to micrographs from damaged interconnects and to strain measurement results obtained by the microDAC measurement method. The application of those combined investigations should help further understanding of failure mechanisms especially in solder joints, and should support further applications for enhancing the thermomechanical reliability of advanced electronic assemblies.