Sven Rzepka

Characterization of self-heating in advanced VLSI interconnect lines based on thermal finite element simulation

In this paper, self-heating of interconnects has been shown to affect the lifetime of next generation integrated circuits significantly more severely than todays. The paper proves the necessity for extending the system of design rules, proposes a thermal design rule, and presents an efficient and quantitatively accurate thermal simulator as tool for the design process.

Three-Dimensional Finite Element Simulation of Electro and Stress Migration Effects in Interconnect Lines

A tool for 3-D modeling of EM and SM in interconnect lines has been developed based on a commercial finite element code. After detailing the approach, we focus on the verification of the simulator by comparing the results of 1-D analytic and FEM simulations, and then we apply the simulator to interconnect line segments with a specified grain structure.

Creep and crack propagation in flip chip SnPb37 solder joints

The lifetime determining event in flip chip packages is the fracture of solder joints. Crack initiation and crack growth in micro solder joints, however, are supposed to differ very much from that of bulky samples of steel, nickel, copper etc. that are usually used in fracture mechanics tests. Hence, the commonly known fracture laws do not hold for FC joints while alternative laws have not been established yet because of a lack of experimental data. The paper presents the results of reversible shear tests on flip chip solder joints under isothermal conditions. Two micro shear testers have been designed and built for this task. One tester is optimized to achieve high precision. In contrast to similar setups, this tester is actively compensated for its finite stiffness. Therefore, it is able to record force displacement hysteresis with a resolution of better than 1 mN and 20 nm force and displacement measurements, respectively. The second tester works very similar but fits in a UHV chamber. In this way, it enables in-situ SEM observations during the test. The results of this study show that the deformation behavior of flip chip solder joints to be more alike to that of bulk samples with a comparable micro structure than it is commonly believed based on published data. The parameters of the determined creep equation indicating what deformation mechanism dominates at what strain rate. The results of the creep tests are compared with that of crack growth experiments. The influence of different deformation mechanisms on the crack growth rate is discussed.

Time-independent plastic behaviour of solders and its effect on FEM simulations for electronics packages

The time-independent behaviour of SnPb37, SnAg3.5 and SnAg4Cu0.5 has been investigated on flip chip solder joints. The test specimen consisted of two silicon chips (3.3 mm in square) bonded by 4 flip chip joints (one at each corner). The Dresden University Micro Shear Tester has been used for the experiments with this type of specimen. In contrast to similar set-ups, it is actively compensated for its finite stiffness. Therefore, it is able to record force displacement hysteresis with a resolution of better than 1 mN and 20 nm, respectively. Based on these measurements, the parameters of the constitutive equations have been evaluated by FEM analysis. This way, the complex stress state within the sample during the test has been considered precisely providing for high accuracy of the parameter extracted. As a typical application, a three point bending experiment has been simulated by FEM applying different constitutive models for the solder material. Comparing the results, it becomes clear: All the three ingredients, i.e., the elastic, the creep, and the time-independent plastic data, are required in the model. Otherwise it would be incomplete and hence insufficient for assisting in the design of todays electronics packages even with respect to the most frequent load cases.

Thermal analysis of the fusion limits of metal interconnect under short duration current pulses

Thermal analysis of the fusion limits of the IC metal under short duration current pulses has been performed using a quadruple level TiN/AlCu/TiN metallization system. A finite element (FE) simulation program has been calibrated to analyze the thermal effects in detail. The program can be used to predict self heating under DC and transient current conditions for various metal levels, geometries and current loading conditions. It is shown both experimentally and using FE simulations that the metal temperatures rise past 1000/spl deg/C before open circuit failure under short duration current pulses. The critical failure current is strongly influenced by the metal thickness, thermal capacity and pulse width. Further, it is shown that the ratio of the critical energy causing open circuit conditions (fusion limit), to the theoretical melt energy increases with scaling. As a result, narrower metal lines can sustain higher current densities before failure.

A finite element study of thermal stress in copper interconnect

Thermally induced stresses are an important reason for voiding failures in interconnects. In this study, thermal stress in copper interconnect lines is investigated with a finite element model. Different from other FEM studies, our model accounts for anisotropic mechanical properties of copper and for different crystallographic orientations of the grains in the copper interconnect line. Thermal stresses simulated this way show that there is a high stress concentration not only at the interconnect/dielectric boundary but also at the grain boundaries. In addition, the different effects of a random grain orientation vs. a strong texture in the interconnect on the stress have been assessed. These simulations are able to explain some of the published experimental data on void nucleation in copper lines.

The Reliability Assessment of Flip Chip Type Solder Joints Based on the Damage Integral Approach

Thermal fatigue of flip-chip solder joints between a chip and chip carrier is a serious reliability concern. Differences in the temperature and/or in the coefficients of thermal expansion between the chip and substrate lead to stresses which may result in fatigue damage and eventual failure of the interconnect. Conventionally, the solder lives have been estimated by a Coffin-Manson type relation. However, this largely empirical approach becomes inadequate when comparing thermal histories that are widely different, as in the cases of accelerated thermal cycling and power cycling. In this study, we use a damage integral approach where the fatigue damage rate is calculated based on the momentary stress and strain (estimated analytically) experienced by the solder joints. The momentary damage is then integrated over the entire loading history to yield total damage at any moment.