J. C. Vildeuil

N-MOSFET oxide trap characterization induced by nitridation process using RTS noise analysis

This paper presents oxide trap characterization of nitrided and non-nitrided gate oxide N-MOSFETs using low frequency noise (LFN) measurements. The identification of defects generated by the gate oxide growth and the nitridation process is carried out using random telegraph signal noise analysis. Significant properties of traps induced by the nitridation process are pointed out. Main trap parameters, such as their nature, capture and emission times, cross-sections, energy levels, and position with respect to the Si/SiO2 interface, are extracted. These results illustrate the potential of noise investigation for oxide characterizations.

Impact of grain number fluctuations in the MOS transistor gate on matching performance

This paper presents a compact model for the gate impact on MOS transistor matching. It is based on the random variations of grain number in the polycrystalline gate. The model is validated by fitting mismatch increase with substrate bias. This study highlights the importance of local polysilicon depletion and gives a better understanding of complex mechanisms that are responsible for MOSFET mismatch.

Can 1/f noise in MOSFETs be reduced by gate oxide and channel optimization?

This contribution addresses several important topics about 1/f noise in MOSFETs for the 65 nm node. We show that a plasma nitridation technique can significantly improve the 1/f noise performances of the device providing that the insulator is thick enough. This result is explained by correlating the 1/f noise magnitude and the nitrogen concentration profile within the gate oxide. In a second time we investigate the effect of dopant dose and species in the substrate as well as the influence of channel orientation (110) and (100).

Response of Correlated Double Sampling CMOS Imager Circuit to Random Telegraph Signal Noise

This paper presents analytical and experimental noise of a correlated double sampling (CDS) readout circuit used in CMOS active pixel image sensors. The work takes into account low frequency noise, mainly random telegraph signal (RTS) noise, in modern MOS transistors with very small geometries. The impact of the source-follower transistor noise power spectral density through CDS is studied. The results allow the determination of the output rms noise versus random telegraph signal noise characteristics. We show that R.T.S. noise of the source-follower is a major factor influencing the circuit output rms noise. Theoretical results are compared with experimental data

Trap competition inducing R.T.S noise in saturation range in N-MOSFETs

A characterization of low frequency noise in submicron N-MOSFETs is presented. For large devices, it is found that 1/f noise results from carrier number fluctuations. The slow oxide interface trap density deduced from noise data is found around 1016 eV-1 cm-3 in agreement with state-of-the-art gate oxides. Submicron devices present R.T.S noise and exhibit three independent active traps in saturation range, from weak to strong inversion. All of these traps have been found as acceptor type centers. Their activity ranges, their maximum of activities and their positions in the oxide from the Si-SiO2 interface have been obtained by the study of emission and capture times against gate voltage. It is shown existing overlap in trap activities for particular gate bias ranges. This overlap is confirmed by the observation of multi level R.T.S in time and frequency domains. For each trap, the number of R.T.S events is explained using the trap occupation probability. Finally, the global R.T.S behavior of devices, including the whole trap activities from weak to strong inversion, could be described using the simple R.T.S model classically used for a single oxide trap. This global study shows a simple method to determine R.T.S impact, and describes perfectly multi-trap activity.

Impact of strained-channel n-MOSFETs with a SiGe virtual substrate on dielectric interface quality evaluated by low frequency noise measurements

We have investigated gate and drain current noise on strained-channel n-MOSFETs with a SiGe virtual substrate and a 12 A thermally nitrided gate oxide using low frequency noise measurements. The power spectral densities (PSD) of the flat-band voltage fluctuations are extracted from both gate and drain current noise. We show that the same oxide trap density profile is involved in drain and gate low frequency noise. A comparison with standard n-MOSFET transistors with the same gate stack process is presented. The flat-band voltage PSD concept is also used to compare both technologies to show that bulk and dielectric quality of strained devices are not degraded with regard to standard n-MOSFETs.

Study of bipolar transistor matching at high current level with various test configurations leading to a new model approach

Matching of bipolar transistors has been characterized for high currents. The predominant impact of access resistance mismatch is clearly demonstrated, and matching models are suggested. Moreover, matching results dependency on test configurations is studied.

Random telegraph signal: A sensitive and nondestructive tool for gate oxide single trap characterization

Abstract This paper presents the electrical characterization of thick and thin SiO2 oxynitride performed by thermal and plasma nitridation processes. The impact of the nitridation technique is investigated using random telegraph signal (RTS) noise analysis. The variation of the gate oxide trap characteristics is determined with respect to the nitridation technique. Significant properties of traps are also pointed out. Main trap parameters, such as their depth with respect to the interface, nature, capture and emission times are extracted. These results illustrate the potential of RTS noise investigation for gate oxide characterizations.

Impact of emitter resistance mismatch on base and collector current matching in bipolar transistors

Bipolar transistor matching is characterized at medium and high current levels using an HF test structure. We demonstrate the predominant impact of emitter resistance mismatch on base and collector current matching at high current. To this end, we simulate base and collector mismatch thanks to the experimental values of emitter access resistance and its variations. The results of these simulations are successfully compared to the experimental data.

Understanding the Carbon Impact on Si/SiGe:C HBT Base Current Mismatch

In this paper, we have investigated the impact of the carbon concentration on bipolar transistor matching at medium current region. Original base current matching results, obtained from the characterization of two carbon concentration splits in a SiGe:C BiCMOS technology, are first discussed and well interpreted by a new base current mismatch physical model. Our assumptions are also confirmed by a matching characterization of bipolar transistors subjected to a hot carrier injection (HCI) stress.