Mathieu Marin

Low frequency noise characterization in 0.13 μm p-MOSFETs. Impact of scaled-down 0.25, 0.18 and 0.13 μm technologies on 1/f noise

Abstract This paper presents an experimental analysis of the noise measurements performed in 0.13 μm technology p-MOS transistors operating from weak to strong inversion in ohmic and saturation regimes. The 1/ f noise origin is interpreted in terms of carrier number with correlated mobility fluctuations. The contribution of the access resistance noise is noticed for large overdrive voltages. The slow oxide trap density N t ( E F ) and the Coulomb scattering noise parameter α s have been extracted. Then the 1/ f noise level in the three scaled-down p-MOSFETs generations (0.25, 0.18 and 0.13 μm) is compared. The variation of the noise parameter values is discussed with respect to the technology node. The highest oxide trap density is obtained for the thinnest gate oxide. It is concluded that the oxide thinning should lead to noise reduction only if the product t ox 2 . N t is taken into consideration. This trend will be significant in future scaled-down MOSFETs.

Effects of body biasing on the low-frequency noise of NMOSFETs from a 130-nm CMOS technology

We investigate the impact of body biasing on the low frequency noise (LFN) performances of NMOS transistors from a transistors 130 nm CMOS technology. The body-to-source voltage VBS was varied from - 0.5 to + 0.5 V for reverse and forward mode substrate biasing. A detailed electrical characterization was performed and the benefits of the body bias analysed in terms of current and maximum transconductance variations. Noise measurements were first performed at low drain bias VDS = 25 mV and VBS = 0 V in order to discuss the noise model. Results are in agreement with the carrier number fluctuation theory. Bulk bias dependence of the LFN was investigated at VDS = VDD = 1.2 V. Significant noise reduction is observed in the subthreshold regime when applying a forward body bias. In strong inversion, the noise level is found to be approximately independent of the substrate bias VBS.

Impact of scaling down on 1/f noise in MOSFETs

An overview of the theoretical 1/f noise models is given. Analytical expressions showing the device geometry and bias dependence of 1/f noise in all conduction regime are summarized. Recent experimental studies on 1/f noise in MOS transistors are presented with special emphasis for PMOS from a 90 nm CMOS technology. Gate and drain noise sources are investigated. It is shown that in subthreshold regime drain current noise agrees with carrier number fluctuation model whereas in strong inversion the evolutions can be described by mobility fluctuation model. Gate current noise shows 1/f and white noise. White noise is very close to shot noise, and we have a quadratic variation of 1/f noise with gate current. Coherence measurements show that the increase of drain noise at high gate biases can be attributed to tunneling effects. Input-referred gate noise and the volume trap density can be used as figure of merit. Discrepancies with the ITRS roadmap are discussed.

Impact of carbon concentration on 1∕f noise and random telegraph signal noise in SiGe:C heterojunction bipolar transistors

The influence of carbon concentration on the low-frequency noise (LF noise) of Si∕SiGe:C∕Si heterojunction bipolar transistors (HBTs) is investigated. When carbon is incorporated into these HBTs, representative noise spectra of the input current spectral density SIB show significant generation-recombination (GR) components. On the other hand, for transistors without carbon incorporation, no GR components were observed. When only 1∕f noise component is observed, the 1∕f noise level is found to be independent of the carbon concentration and the associated figure of merit of the normalized noise magnitude KB has a very good value of ∼4×10−10μm2. In order to relate the 1∕f noise and the high-frequency performance of the transistor, we studied and modeled the figure of merit defined as the ratio fc∕fT (fc is the low-frequency corner frequency and fT the unity current-gain frequency). Then we performed a detailed analysis of the GR components associated with the presence of the carbon. We found that the observe...

Impact of Inside Spacer Process on Fully Self-Aligned 250 GHz SiGe:C HBTs Reliability Performances: a - Si vs. Nitride.

Abstract A critical process aspect of the bipolar device is the oxide isolation between the emitter and the extrinsic base. Indeed, it is a well known fact that the emitter–base junction degradation is mainly due to interface states generation underneath oxide spacer. This study demonstrates the large impact of the inside spacer process in fully-self aligned high speed HBT on its reliability. Several types of electrical stress have been investigated and the stress-induced degradation compared for nitride and a-Si (amorphous silicon) spacers. Aging results coupled with noise measurements and TCAD simulations allowed to explain the different observed behaviors, finally concluding on the significantly higher reliability performances of devices processed with a-Si spacers.

Mismatch Measure Improvement Using Kelvin Test Structures in Transistor Pair Configuration in Sub-Hundred Nanometer MOSFET Technology

In this paper, a mismatch test structure in standard pair configuration using Kelvin method is introduced to better estimate the MOSFET local electrical fluctuations in sub-hundred nanometer technologies. Considering this test structure configuration, the impact of extern access connections on threshold voltage (Vt), gain factor (ß) and drain current (ID) mismatch extraction is investigated. To exhibit the impact of this parameter, the Vt and ß are then extracted using extrapolation method. We demonstrate that the variability of access connections does not impact Vt mismatch whereas drain current matching is underestimated without Kelvin method.

Impact of Technological Parameters on the Low Frequency Noise of Advanced Heterojunction Bipolar Transistors

Usually, the 1/f noise sources in heterojunction bipolar transistors (HBTs) are located in the intrinsic emitter‐base (E‐B) volume, either in the E‐B junction space charge region or at the polycrystalline‐silicon/monocrystalline‐silicon interface in the neutral emitter layer. In this paper, to probe more accurately the location of the noise sources responsible for the 1/f noise, investigations on different HBTs fabricated with different technological parameters are undertaken. First, we have shown that carbon content has a negligible influence on 1/f noise level, but for high carbon content significant generation‐recombination (G‐R) noise components appear. Second, by studying influence of the emitter‐base junction depth, we have shown that the 1/f noise sources are located at the polycrystalline‐silicon/monocrystalline‐silicon interface. Using statistical estimators, we have studied and modelled the dispersion of the 1/f noise. It was found that the dispersion in the noise level increases as the inverse ...

Modeling the Mismatch of High-k MIM Capacitors

In this contribution we investigate the matching properties of modern high-k metal-insulator-metal (MIM) capacitors. In particular, we derive a compact physics-based model in order to explain the observed geometry dependence of mismatch. This model is successfully applied to MIM devices processed with Ta₂O₅ and AI₂O₃ as dielectrics.

Coupled Approach for Reliability Study of Fully Self Aligned SiGe: C 250GHz HBTs

High performance bipolar transistors were investigated under both reverse and forward stress conditions. Although classical hot-carrier induced degradation has been shown in reverse mode, the results obtained under forward conditions were not in line with those reported for previous device generation. Indeed, the coupled approach using low frequency noise spectra measurements and reliability studies show a relaxation of the pre-existing and/or created defects during stress. Moreover, coexistence of both classical Shockley-Read-Hall recombination and unusual trap-assisted tunnelling is clearly demonstrated and confirmed by TCAD simulations.

Understanding the Carbon Impact on Si/SiGe:C HBT Base Current Mismatch

In this paper, we have investigated the impact of the carbon concentration on bipolar transistor matching at medium current region. Original base current matching results, obtained from the characterization of two carbon concentration splits in a SiGe:C BiCMOS technology, are first discussed and well interpreted by a new base current mismatch physical model. Our assumptions are also confirmed by a matching characterization of bipolar transistors subjected to a hot carrier injection (HCI) stress.