J. Chung

A model for hot-electron-induced MOSFET linear-current degradation based on mobility reduction due to interface-state generation

A simple model for the hot-electron degradation of MOSFET linear-current drive is developed on the basis of the reduction of the inversion-layer mobility due to the generation of interface states. The model can explain the observed dependence of the device hot-electron lifetime on the effective channel length and oxide thickness by taking into account both the relative nonscalability of the localized damage region and the dependence of the linear-current degradation on the effective vertical electric field E/sub eff/. The model is verified for deep-submicrometer non-LDD n-channel MOSFETs with L/sub eff/=0.2-1.5 mu m and T/sub ox/=3.6-21.0 nm. From the correlation between linear-current and charge-pumping degradation, the scattering coefficient alpha , which relates the number of generated interface states to the corresponding amount of inversion-layer mobility reduction, can be extracted and its dependence on E/sub eff/ determined. Using this linear-current degradation model, existing hot-electron lifetime prediction models are modified to account explicitly for the effects of L/sub eff/ and T/sub ox/. >

Deep-submicrometer MOS device fabrication using a photoresist-ashing technique

A photoresist-ashing process has been developed which, when used in conjunction with conventional g-line optical lithography, permits the controlled definition of deep-submicrometer features. The ultrafine lines were obtained by calibrated ashing of the lithographically defined features in oxygen plasma. The technique has been successfully used to fabricate MOSFETs with effective channel length as small as 0.15 mu m that show excellent characteristics. An NMOS ring oscillator with 0.2- mu m devices has been fabricated with a room-temperature propagation delay of 22 ps/stage. Studies indicate that the thinning is both reproducible and uniform so that it should be usable in circuit as well as device fabrication. Since most polymer-based resist materials are etchable with an oxygen plasma, the basic technique could be extended to supplement other lithographic processes, including e-beam and X-ray processes, for fabricating both silicon and nonsilicon devices and circuits.<<ETX>>

Low-voltage hot-electron currents and degradation in deep-submicrometer MOSFETs

Hot-electron currents and degradation in deep submicrometer MOSFETs at 3.3 V and below are studied. Using a device with L/sub eff/=0.15 mu m and T/sub ox/=7.5 nm, substrate current is measured at a drain bias as low as 0.7 V; gate current is measured at a drain bias as low as 1.75 V. Using the charge-pumping technique, hot-electron degradation is also observed at drain biases as low as 1.8 V. These voltages are believed to be the lowest reported values for which hot-electron currents and degradation have been directly observed. These low-voltage hot-electron phenomena exhibit similar behavior to hot-electron effects present at higher biases and longer channel lengths. No critical voltage for hot-electron effects (such as the Si-SiO/sub 2/ barrier height) is apparent. Established hot-electron degradation concepts and models are shown to be applicable in the low-voltage deep submicrometer regime. Using these established models, the maximum allowable power supply voltage to insure a 10-year device lifetime is determined as a function of channel length (down to 0.15 mu m) and oxide thicknesses. >

Performance and reliability design issues for deep-submicrometer MOSFETs

Device design constraints, such as threshold voltage variation due to short-channel and drain-induced-barrier-lowering effects, off-state leakage current due to punchthrough and gate-induced drain leakage, hot-carrier effects such as hot-electron degradation and avalanche breakdown, and time-dependent dielectric breakdown, are examined. The current-driving capability, ring-oscillator switching speed, and small-signal voltage gain are examined. The impact that each of these factors has on the allowable choice of MOSFET channel length, oxide thickness, and power supply voltage is examined. Based on experimental results, a set of design curves, using a set of typical performance and reliability criteria, is presented for deep-submicrometer nonlightly doped drain (non-LDD) n-channel devices. From these curves, the relative importance of each particular performance/reliability mechanism for a given technology and design criteria can be determined. Because the performance and reliability issues addressed are also relevant to other MOSFET technologies, the design guidelines can also be extended to other technologies, including p-channel and LDD devices. >

The effects of hot-electron degradation on analog MOSFET performance

Many analog MOSFET performance parameters are found to be very sensitive to hot-electron stress, especially compared with digital parameters that are normally monitored. Drain output resistance degradation is characterized in detail using existing hot-electron reliability concepts and lifetime prediction models. The impact of drain output resistance degradation on the performance of a CMOS single-ended output differential amplifier is found to be a sensitive function of the particular circuit design and operating conditions.<<ETX>>

The effects of low-angle off-axis substrate orientation on MOSFET performance and reliability

The effects of low-angle off-axis substrate orientation on MOSFET performance and reliability are examined. When wafers are tilted off axis from 0 degrees to 8 degrees around the axis, two principal effects are observed. First, for current flow normal to the axis of rotation, inversion-layer mobility is lower than for current flow in the parallel direction. This mobility difference is due to anisotropy in the inversion-layer effective mass as well as increased surface roughness in the normal compared with the parallel direction. Second, as the substrate is rotated off axis, the susceptibility of gate oxide to defect-related breakdown is enhanced. The off-axis surface exhibits increased surface roughness, which promotes nonuniform oxidation and can significantly degrade VLSI reliability. >

The development and application of a SiSiO2 interface-trap measurement system based on the staircase charge-pumping technique

Abstract An automated Siue5f8SiO 2 interface-trap measurement system based on the staircase charge-pumping technique is developed. This system can perform interface-trap density ( D it ) energy distribution measurements directly on n - and p -channel submicrometer MOSFETs without requiring complex transient recombination modeling. It is demonstrated that the staircase charge-pumping technique is capable of characterizing interface-trap densities as low as 10 9 cm −2 eV −1 as well as detecting trap states within 50 meV of the conduction-band edge. The technique is also sensitive to recombination time constants (τ) ranging over four orders of magnitude. In this study, experimental evidence is presented confirming several significant assumptions used in the staircase charge-pumping technique. Verification is provided of the establishment of quasi-equilibrium, the independence between trapping and detrapping processes, and the justification of neglecting edge effects and parasitic current components. Criteria are presented outlining the regions of validity for utilizing staircase charge pumping. Applications in the monitoring of oxide degradation due to Fowler-Nordheim tunneling and hot-electron injection are demonstrated.

A new LDD structure: total overlap with polysilicon spacer (TOPS)

The total overlap with polysilicon spacer (TOPS) structure, a fully overlapped lightly doped drain (LDD) structure, is discussed. The TOPS structure achieves full gate overlap of the lightly doped region with simple processing. TOPS devices have demonstrated superior performance and reliability compared to oxide-spacer LDD devices, with an order of magnitude advantage in current degradation under stress for the same initial current drive or 30% more drive for the same amount of degradation. TOPS devices also show a much smaller sensitivity to n/sup -/ dose variation than LDD devices. Gate-induced drain leakage is reported for the first time in fully overlapped LDD devices.<<ETX>>

Hot-electron currents in deep-submicrometer MOSFETs

A comprehensive study of hot-electron-induced substrate and gate currents in deep-submicrometer MOSFETs is presented. The substrate- and gate-current characteristics for devices with channel lengths as small as 0.2 mu m and oxide thickness as thin as 55 AA are examined. Implications for MOSFET reliability and EPROM programming are discussed. In the deep-submicrometer regime, established hot-electron concepts and models are found to be applicable; however, consideration of the finite depth of the current path and current-crowding-induced weak gain control becomes much more important. With these modifications, physical analytical models for substrate and gate currents are developed and verified for deep-submicrometer devices.<<ETX>>

Correlation between channel hot-electron degradation and radiation-induced interface trapping in MOS devices

A correlation between channel hot-carrier induced degradation is conventional-drain NMOSFETS and radiation-induced transconductance (g/sub m/) degradation is described. The device lifetime, tau /sub HE/, was proportional to the 1.5 power D)/sub EFF/, where D/sub EFF/ is the radiation dose when Delta g/sub m//g/sub m/=0.5. These results indicate that radiation-induced interface trapping is a strong indicator of hot-electron-device lifetime. The proposed radiation test can be applied to devices with both radiation-hard and radiation-soft field oxide. Initial results on lightly-doped-drain (LDD) devices indicate that correlation between hot-electron degradation and radiation-induced interface trapping is strongly dependent on the design of the LDD. >