Tung-Yi Chan

Hot-electron-induced MOSFET degradation—Model, monitor, and improvement

Evidence suggests that MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. This critical energy and the observed time dependence is explained with physical model involving the breaking of the ≡ Si<inf>s</inf>H bonds. The device lifetime τ is proportional to<tex>I_{sub}^{-2.9}I_{d}^{1.9}\Delta V_{t}^{1.5}</tex>. If I<inf>sub</inf>is large because of small<tex>L</tex>or large V<inf>d</inf>, etc., τ will be small. I<inf>sub</inf>(and possibly light emission) is thus a powerful predictor of τ. The proportionality constant has been found to vary by a factor of 100 for different technologies, offering hope for substantially better reliability through future improvements in dielectric /interface technologies. A simple physical model can relate the channel field E<inf>m</inf>to all the device parameters and bias voltages. Its use in interpreting and guiding hot-electron scaling are described. LDD structures can reduce E<inf>m</inf>and I<inf>sub</inf>and, when properly designed, reduce device degradation.

Threshold voltage model for deep-submicrometer MOSFETs

The threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep-submicrometer range has been investigated. Experimental data show that in the very-short-channel-length range, the previously reported exponential dependence on channel length and the linear dependence on drain voltage no longer hold true. A simple quasi-two-dimensional model is used, taking into account the effects of gate oxide thickness, source/drain junction depth, and channel doping, to describe the accelerated V/sub th/ on channel length due to their lower drain-substrate junction built-in potentials. LDD devices also show less V/sub th/ dependence on drain voltage because the LDD region reduces the effective drain voltage. Based on consideration of the short-channel effects, the minimum acceptable length is determined. >

A true single-transistor oxide-nitride-oxide EEPROM device

A novel single-transistor EEPROM device using single-polysilicon technology is described. This memory is programmed by channel hot-electron injection and the charges are stored in the oxide-nitride-oxide (ONO) gate dielectric. Erasing is accomplished in milliseconds by applying a positive voltage to the drain plus an optional negative voltage to the gate causing electron tunneling and/or hot-hole injection due to the deep-depletion-mode drain breakdown. Since the injection and storage of electrons and holes are confined to a short region near the drain, the part of the channel near the source maintains the original positive threshold voltage even after repeated erase operation. Therefore a select transistor, separate or integral, is not needed. Because oxide layers with a thickness larger than 60 Å are used, this device has much better data retention characteristics than conventional MNOS memory cells. This device has been successfully tested for WRITE/ERASE endurance to 10000 cycles.

Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement

Evidence suggests that MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. This critical energy and the observed time dependence is explained with a physical model involving the breaking of the = Si/sub s/H bonds. The device lifetime /spl tau/ is proportional to...

A simple method to characterize substrate current in MOSFET's

Experimental verification of substrate current characteristics is thoroughly carried out. V<inf>DS</inf>- V<inf>DSAT</inf>, instead of V<inf>DS</inf>, is shown to be the driving force of all hot-electron effects. A simple relationship between substrate current and V<inf>DS</inf>- V<inf>DSAT</inf>is found. This relationship provides a convenient tool to characterize the substrate current or the channel electric field, and, hence, all hot-electron effects. Measurements of I<inf>SUB</inf>/I<inf>D</inf>and V<inf>DS</inf>- V<inf>DSAT</inf>at two bias points and any one channel length are sufficient to fully characterize the substrate currents for all channel lengths V<inf>DS</inf>s and V<inf>G</inf>s for a given technology.

Dependence of channel electric field on device scaling

It has been shown previously that the maximum channel electric field E<inf>m</inf>in a MOSFET is the most important parameter relating to all hot-electron effects and that E<inf>m</inf>can be represented as (<tex>V_{DS} - V_{DSAT})/l</tex>, where<tex>l</tex>may be regarded as the effective length of the velocity-saturation region. The dependence of l on device geometries and process parameters is investigated in this letter. From both experiment and two-dimensional (2-D) simulation, it is found that E<inf>m</inf>has a form of (<tex>V_{DS} - V_{DSAT})/ 0.22T\min{ox}\max{1/3}X\min{j}\max{1/2}</tex>. Channel length affects the saturation voltage, thus influencing the maximum channel electric field. The scaling of oxide thickness and junction depth, however, often has even greater effects on channel field. This semiempirical model of E<inf>m</inf>agrees with E<inf>m</inf>deduced from I<inf>SUB</inf>within about 5 percent; it can predict I<inf>SUB</inf>, which has been empirically correlated with hot-electron degradations.

Deep-submicrometer MOS device fabrication using a photoresist-ashing technique

A photoresist-ashing process has been developed which, when used in conjunction with conventional g-line optical lithography, permits the controlled definition of deep-submicrometer features. The ultrafine lines were obtained by calibrated ashing of the lithographically defined features in oxygen plasma. The technique has been successfully used to fabricate MOSFETs with effective channel length as small as 0.15 mu m that show excellent characteristics. An NMOS ring oscillator with 0.2- mu m devices has been fabricated with a room-temperature propagation delay of 22 ps/stage. Studies indicate that the thinning is both reproducible and uniform so that it should be usable in circuit as well as device fabrication. Since most polymer-based resist materials are etchable with an oxygen plasma, the basic technique could be extended to supplement other lithographic processes, including e-beam and X-ray processes, for fabricating both silicon and nonsilicon devices and circuits.<<ETX>>

A novel high-speed, 5-volt programming EPROM structure with source-side injection

A novel source-side injection EPROM (SIEPROM) structure [1] capable of 5-volt only, high speed programming is described. The cell is an asymmetrical n-channel stacked-gate MOSFET, with a short weak gate-control region introduced close to the source. Under high gate bias, a strong channel electric field is created in this local region even at a relatively low drain voltage. Furthermore, the gate oxide field in this region is favorable for hot-electron injection into the floating gate. As a result, a programming speed of 10 µs at a drain voltage of 5 volts has been demonstrated. Also, a soft-write endurance time of 10 years with a read current larger than 100 µA per µm width can be readily achieved.

A CV technique for measuring thin SOI film thickness

A technique is developed to measure silicon-on-insulator (SOI) silicon device film thickness using a MOSFET. The method is based on CV measurements between gate and source/drain at two different back-gate voltages. The SOI devices used in this study were n/sup +/ polysilicon gate n-channel MOSFETs fabricated with modified submicrometer CMOS technology on SIMOX (separation by implanted oxygen) wafers. The SIMOX wafers were implanted with a high dose of oxygen ions (10/sup 18/ cm/sup -2/) at 200 keV and subsequently annealed at 1230 degrees C. The NMOS threshold boron implant dose is 2*10/sup 12/ cm/sup -2/. This method is simple, nondestructive, and no special test structure is needed. Using this technique, SOI film thickness mapping was made on a finished wafer and a thickness variation of +or-150 AA was found.<<ETX>>

Asymmetrical characteristics in LDD and minimum-overlap MOSFET's

An asymmetrical drain, substrate, and gate current phenomenon with respect to drain-source reversal in short-channel lightly doped-drain (LDD) and minimum-overlap MOSFET has been observed. By controlled device fabrication splits, it is confirmed that these asymmetrical device characteristics are caused by the 7° off-axis drain-source implant which creates different degrees of offset between the gate edge and the source-drain junctions. The offset degrades the I-V characteristics. Substrate and gate current asymmetries are studied by analyzing the channel electrical field using two-dimensional device simulations. High-channel field at the source end is proposed to explain the second hump in the double-humped substrate current characteristic and the strong gate current injection when the devices are operated with the nonoverlap side as the source. One way to avoid the shadowing effect at ion implantation is to etch the poly-gate side wall to a small positive level angle.