J.E. Brewer

On-chip antennas in silicon ICs and their application

The feasibility of integrating antennas and required circuits to form wireless interconnects in foundry digital CMOS technologies has been demonstrated. The key challenges including the effects of metal structures associated with integrated circuits, heat removal, packaging, and interaction between transmitted and received signals, and nearby circuits appear to be manageable. This technology can potentially be applied for implementation of a true single-chip radio for general purpose communication, on-chip and inter-chip data communication systems, RFID tags, RF sensors/radars, and others.

Extending the road beyond CMOS

The accelerating pace of CMOS scaling is rapidly approaching the fundamental limits of MOSFET performance, even as the projected size of a high-performance and manufacturable MOSFET technology is currently being extended with growing confidence to the 22-nm node (featuring a 9-nm physical gate length). The new 2001 International Technology Roadmap for Semiconductors currently projects the industry to reach this node in 2016. However, this forecast assumes the traditional industry node-cycle cadence of a quadrupling of the number of transistors every three years for DRAMS and a return to the three-year cycle in 2004 for MPUs and ASICs. During the past several years the node cycles for MPUs have been accelerated to occur within two-year periods. This pace will bring the microelectronics industry to the end of silicon CMOS technology scaling sometime not later than 2016, and maybe as soon as 2010. The new Emerging Technologies section of the 2001 ITRS offers guidance on both sides of this problem: nanoelectronics for memory, logic, and information-processing architectures could possibly extend the time frame of the ITRS beyond CMOS.

Communication Using Antennas Fabricated in Silicon Integrated Circuits

The feasibility of integrating compact antennas and required circuits for implementing wireless interconnections in foundry digital CMOS technologies has been demonstrated. A 3-mm long zigzag dipole antenna on a 20-Omega-cm substrate should have efficiency up to approximately 25% at 24 GHz and cost 1-2 cents. These antennas can be used to implement a radio for 100-kb/s communication up to about 10 m. By lowering the operation frequency to 5.8 GHz and using a monopole structure, which occupies approximately 30% more area, the communication range can be increased by three times or more. This technology, as well as in a true single-chip radio, can be used for intra- and inter-chip data communication, intra- and inter-chip clock distribution, beacons, radars, RFID tags, and contactless high-frequency testing.

Integrated antennas on silicon substrates for communication over free space

This letter reports the feasibility of using 2-mm-long on-chip antennas for communication over free space. Integration of antennas into radio frequency integrated circuits (RFICs) eliminates external transmission line connections and sophisticated packaging, which should lower the cost of wireless systems operating above 10 GHz. Mobile microwave probe stands have been developed for measurements at varying antenna pair separations. Antenna-pair gains for 2-mm-long integrated zigzag dipole antennas fabricated on 20-/spl Omega/-cm silicon substrates have been characterized near 24 GHz for separations up to 15 m. The antenna-pair gains show R/sup -2/ dependence up to /spl sim/4-5 m. The antennas were found to be sufficient for use up to 5 m and possibly larger separations.

Emerging Nanoscale Memory and Logic Devices: A Critical Assessment

This article presents the ERD Working Groups collective judgment with respect to the long-term potential of nanoscale memory and logic devices to replace silicon-based CMOS logic or baseline memory technology. It does not judge their potential to supplement or complement CMOS. The intent is thus prescriptive, not prescriptive: to provide a technically grounded, objective benchmark for emerging research memory and logic devices.

Boolean Logic and Alternative Information-Processing Devices

Emerging research device technologies might first appear in special applications that can extend conventional general-purpose processors along one of several axes. These applications could optimize the performance of future workloads such as recognition, mining, and synthesis by using the unique nonlinear output characteristics associated with the emerging research devices. However, a new device technology might emerge that, by way of first supplementing conventionally scaled CMOS, could eventually offer a highly scalable new information- processing paradigm.

Memory technology for post CMOS era

One of the tasks of the International Technology Roadmap for Semiconductors (ITRS) Emerging Research Devices (ERD) Technology Working Group (TWG) is to seek out memory technologies presented in the research literature and weigh whether they have the potential to serve in 22-nm and smaller IC generations. The motive for this effort is to develop data that can help guide research investment decisions. In 2004, the ERD TWG summarized some quantitative attributes of four alternative memory approaches, and developed a potential/risk score for each. While this effort falls far short of identifying a specific technology, it is at least a beginning. This article describes the nature of the challenge and reports initial study results.

Silicon Integrated Circuits Incorporating Antennas

The feasibility of integrating antennas and required circuits to form wireless interconnects in foundry digital CMOS technologies has been demonstrated. The key challenges including the effects of metal structures associated with integrated circuits, heat removal, packaging, and interaction of transmitted and received signals with nearby circuits appear to be manageable. This technology can potentially be used for intra and inter-chip interconnection, and implementation of true single chip radios, beacons, radars, RFID tags and others, as well as contact-less high frequency testing

10/spl times/ improvement of power transmission over free space using integrated antennas on silicon substrates

This paper reports the techniques for improving the characteristics of integrated antennas fabricated on silicon substrates for communications over air. Using these, the pair gain (G/sub a/) of antennas on 20-/spl Omega/-cm substrates has been improved by /spl sim/10/spl times/ over the previously reported result. Lastly, the possibility of realizing single chip radios with integrated antennas for communication over air is suggested by picking up, amplifying, and frequency dividing a 15-GHz sine wave transmitted from a 2-mm long on-chip antenna located 40 cm away using a packaged clock receiver with a 2-mm long on-chip zigzag antenna.

Emerging Research Architectures

Morphic architectures embrace a broad class of mixed-signal systems that focus on a particular application and draw inspiration for their structure from the application. In some cases, processing is carried out in the analog domain, offering orders-of-magnitude improvement in performance and power dissipation, albeit with reduced accuracy. The emergence of many-core (symmetric and asymmetric) architectures has become an established industry trend. With high-end microprocessor architecture moving to a multicore format, dual-core products have become available commercially and quad-core chips are entering the marketplace. Indeed, a recently announced 80-core experimental chip heralds a new milestone. Several other companies now produce multicore-like devices that some call next-generation field-programmable gate arrays (FPGAs). Specifically, these companies are implementing field- programmable object array (FPOA) technology, which consists of object arrays that are simple processors and other support objects such as memory.